Commit src/still_alive/imported.h instead of ignoring it. The importer now
writes a source reference (SDSkyKlouD/still-alive-web) and a disclaimer
(Jonathan Coulton / Valve, personal non-commercial use, not affiliated) at
the top of the file; the README carries the same disclaimer.
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
- src/still_alive: timed console text, typed scrolling credits and ASCII art,
laid out for 512x256 (41x31 console, 41x9 credits, 41x20 picture).
Plays placeholder content unless imported.h exists.
- tools/import_still_alive.py: generates the git-ignored imported.h (text,
timing, art, credits) from SDSkyKlouD/still-alive-web.
- platformio.ini: envs still_alive (default) and esp32dev (test images,
moved to src/test_images).
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Uninverted, the rising BCK edge landed on the boundary between byte pairs,
so the panel sampled data mid-change and the image jittered. Inverted, the
edge sits mid-pair; verified stable on the panel. Also note the row-stripe
brightness drift as an open item.
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
PCNT measurement showed I2S0 BCK (VCLK) rising once per two bytes in 8-bit
LCD mode, so the panel saw every other byte. Each VCLK is now two identical
bytes at a 10 MHz byte rate (VCLK 5 MHz). The doubled ~142 KB stream is
allocated as 38 per-descriptor chunks.
The test sketch now cycles through 12 labelled test images.
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
The datasheet numbers columns from 1 (Fig. 3: "row 1", "Last pixel
(512 / 256)") and puts odd columns on TVID, so x = 0 (column 1) now
goes to TVID and x = 1 to VID; the encoder had them swapped.
README wiring now lists the J1/J2 pins and power rails from Table 1,
the 5 V buffer, and a pull-down on ENABLE so the panel stays off while
the ESP32 boots without VCLK. encodeRow() documents its T4/T5 margins.
docs/README.md open items are regrouped into done, hardware checks and
software work. main.cpp counts seconds, not frames.
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
The datasheet (docs/datasheet, Planar 020-0354-00A) is now stated as the
source of truth. Two-bit mode is PS1 jumper 2 (DCONFIG) removed
(Table 3), not a generic "mode jumper". The README timing table now lists
the Table 5/6 limits beside our values, and the notes add T1-T8, the
8 ns setup/hold from Figure 4 and the input levels from Table 4.
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
startI2S() sets up I2S0 in 8-bit parallel (LCD) mode at 5 MHz
(PLL_D2 160 MHz / 32, BCK div 1), routes stream bits 0..3 to
VID/TVID/HS/VS via I2S0O_DATA_OUT16+n and BCK to VCLK, and loops
DMA over an 18-descriptor chain of whole lines. stopI2S() stops TX,
returns the pins to GPIO low and frees the chain.
encodeRow() now stores clock c at c ^ 2 to match the 8-bit mode
byte order (bytes 2, 3, 0, 1 per word, as in bitluni's ESP32Lib).
Builds with no warnings; not yet checked on hardware.
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
PlatformIO skeleton (esp32dev, Arduino, Adafruit GFX) with a local EL512
library: EL512Panel (1 bpp framebuffer, two-bit-mode row encoder, I2S DMA
refresh stub) and EL512_GFX (Adafruit_GFX subclass). Adds a test sketch,
pin map, README with wiring and timing, and moves the datasheet to
docs/datasheet/.
Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
mangavalkandClaude Opus 5.5