mangavalkandClaude Opus 5.5
dbc1f0041f
- Design docs: 12 V DC power supply, safety and bring-up, ESP32 interface, BOM - PSU schematic (schemdraw) and KiCad 10 carrier-board project with HV net classes - ESP32 PlatformIO firmware skeleton with HV watchdog toggle - Reference schematic of the Stern 520-5138-00 display PSU Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
67 lines
2.9 KiB
Markdown
67 lines
2.9 KiB
Markdown
# KiCad project: PSU carrier board
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Open `plasma_dmd_psu.kicad_pro` in KiCad 10.
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The board carries the fuses, the HV watchdog, both regulators (copied from Stern 520-5138-00) and
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the connectors. The AliExpress modules sit **off-board** and connect through Phoenix 5.08 mm screw terminals:
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| Connector | Goes to | Pins |
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|---|---|---|
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| J1 | 12 V DC brick | +12V, GND |
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| J3 | Mini560 5 V buck | IN+, IN−, OUT+, OUT− |
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| J4 | Relay module | VCC, GND, IN, COM, NO |
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| J5 | NCH6100HV #1 (set 90 V) | VIN, GND, HV+ |
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| J6 | Isolated DC-DC input | VIN, GND |
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| J7 | NCH6100HV #2 (set 130 V) output | HV+ (→ GND), GND (→ −130 V raw) |
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| J8 | ESP32 | 5V, GND, GPIO21 (watchdog) |
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| J2 | Panel power, Molex KK-396 8-pin | Stern CN2 order: 1 −112V, 2 −100V, 3 key, 4–5 GND, 6 +5V, 7 +12V (via JP1), 8 +65V |
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Wire the isolated DC-DC output straight to NCH6100HV #2's input, off-board. Both float at −130 V.
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> ⚠️ **J2 pinout is a placeholder.** It follows the Stern supply, not necessarily your WPC panel.
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> Map it to your panel before you plug anything in.
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## Files
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| File | What |
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|---|---|
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| `gen_kicad.py` | Generates the schematic and the project's net classes from the `PARTS` table. **The source of truth.** |
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| `check_netlist.py` | Exports the netlist with kicad-cli and checks every pin against `PARTS` |
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| `plasma_dmd_psu.kicad_sch` | Generated schematic (labels-per-pin style: connectivity is by net label) |
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| `plasma_dmd_psu.pdf` | Plot of the schematic |
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```bash
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python hardware/kicad/gen_kicad.py
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python hardware/kicad/check_netlist.py
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```
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Re-running `gen_kicad.py` **overwrites the schematic**. Either keep editing `PARTS` and regenerate, or
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stop using the generator once you start editing the schematic in KiCad.
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## Net classes (already in the project)
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| Class | Nets | Clearance | Track |
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|---|---|---|---|
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| HV | +90V_RAW, +65V, −130V_RAW, −112V, −100V, HVP/HVN_MOD and all regulator internals | **3.0 mm** | 0.6 mm |
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| Power | GND, +12V*, +5V, +12V_PANEL | 0.3 mm | 1.0 mm |
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| Default | Watchdog signals | 0.25 mm | 0.4 mm |
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## Making the PCB
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1. Open the PCB editor and choose **Tools → Update PCB from Schematic** (F8). All footprints arrive with ratsnest.
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2. Draw the board outline on `Edge.Cuts`.
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3. Placement tips:
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- Keep the HV area (J5/J7, F4/F5, regulator, J2) on one side and the 12 V/5 V/watchdog on the other.
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- Leave room for TO-220 heatsinks on Q3, Q5 and Q6. R13 (5 W) runs warm.
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- Consider routed slots between the HV and low-voltage areas.
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4. Run DRC. The HV class enforces 3 mm to everything.
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## Verified so far
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- The schematic loads in KiCad 10.0.6, and ERC reports 0 violations.
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- `check_netlist.py`: all 122 pins sit on the intended nets (31 nets).
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- All symbols and footprints come from the KiCad 10 standard libraries.
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- Transistor pinouts match the footprints: MJE15030/31 are B-C-E (TO-220); MPSA42/92 are E-B-C (TO-92); 2N7000 is S-G-D.
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**Not verified:** the circuit itself on real hardware, and the module current ratings.
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