# KiCad project: PSU carrier board

Open `plasma_dmd_psu.kicad_pro` in KiCad 10.

The board carries the fuses, the HV watchdog, both regulators (copied from Stern 520-5138-00) and
the connectors. The AliExpress modules sit **off-board** and connect through Phoenix 5.08 mm screw terminals:

| Connector | Goes to | Pins |
|---|---|---|
| J1 | 12 V DC brick | +12V, GND |
| J3 | Mini560 5 V buck | IN+, IN−, OUT+, OUT− |
| J4 | Relay module | VCC, GND, IN, COM, NO |
| J5 | NCH6100HV #1 (set 90 V) | VIN, GND, HV+ |
| J6 | Isolated DC-DC input | VIN, GND |
| J7 | NCH6100HV #2 (set 130 V) output | HV+ (→ GND), GND (→ −130 V raw) |
| J8 | ESP32 | 5V, GND, GPIO21 (watchdog) |
| J2 | Panel power, Molex KK-396 8-pin | Stern CN2 order: 1 −112V, 2 −100V, 3 key, 4–5 GND, 6 +5V, 7 +12V (via JP1), 8 +65V |

Wire the isolated DC-DC output straight to NCH6100HV #2's input, off-board. Both float at −130 V.

> ⚠️ **J2 pinout is a placeholder.** It follows the Stern supply, not necessarily your WPC panel.
> Map it to your panel before you plug anything in.

## Files

| File | What |
|---|---|
| `gen_kicad.py` | Generates the schematic and the project's net classes from the `PARTS` table. **The source of truth.** |
| `check_netlist.py` | Exports the netlist with kicad-cli and checks every pin against `PARTS` |
| `plasma_dmd_psu.kicad_sch` | Generated schematic (labels-per-pin style: connectivity is by net label) |
| `plasma_dmd_psu.pdf` | Plot of the schematic |

```bash
python hardware/kicad/gen_kicad.py
python hardware/kicad/check_netlist.py
```

Re-running `gen_kicad.py` **overwrites the schematic**. Either keep editing `PARTS` and regenerate, or
stop using the generator once you start editing the schematic in KiCad.

## Net classes (already in the project)

| Class | Nets | Clearance | Track |
|---|---|---|---|
| HV | +90V_RAW, +65V, −130V_RAW, −112V, −100V, HVP/HVN_MOD and all regulator internals | **3.0 mm** | 0.6 mm |
| Power | GND, +12V*, +5V, +12V_PANEL | 0.3 mm | 1.0 mm |
| Default | Watchdog signals | 0.25 mm | 0.4 mm |

## Making the PCB

1. Open the PCB editor and choose **Tools → Update PCB from Schematic** (F8). All footprints arrive with ratsnest.
2. Draw the board outline on `Edge.Cuts`.
3. Placement tips:
   - Keep the HV area (J5/J7, F4/F5, regulator, J2) on one side and the 12 V/5 V/watchdog on the other.
   - Leave room for TO-220 heatsinks on Q3, Q5 and Q6. R13 (5 W) runs warm.
   - Consider routed slots between the HV and low-voltage areas.
4. Run DRC. The HV class enforces 3 mm to everything.

## Verified so far

- The schematic loads in KiCad 10.0.6, and ERC reports 0 violations.
- `check_netlist.py`: all 122 pins sit on the intended nets (31 nets).
- All symbols and footprints come from the KiCad 10 standard libraries.
- Transistor pinouts match the footprints: MJE15030/31 are B-C-E (TO-220); MPSA42/92 are E-B-C (TO-92); 2N7000 is S-G-D.

**Not verified:** the circuit itself on real hardware, and the module current ratings.