Plasma-DMD/hardware/kicad/README.md

KiCad project: PSU carrier board

Open plasma_dmd_psu.kicad_pro in KiCad 10.

The board carries the fuses, the HV watchdog, both regulators (copied from Stern 520-5138-00) and the connectors. The AliExpress modules sit off-board and connect through Phoenix 5.08 mm screw terminals:

Connector	Goes to	Pins
J1	12 V DC brick	+12V, GND
J3	Mini560 5 V buck	IN+, IN−, OUT+, OUT−
J4	Relay module	VCC, GND, IN, COM, NO
J5	NCH6100HV #1 (set 90 V)	VIN, GND, HV+
J6	Isolated DC-DC input	VIN, GND
J7	NCH6100HV #2 (set 130 V) output	HV+ (→ GND), GND (→ −130 V raw)
J8	ESP32	5V, GND, GPIO21 (watchdog)
J2	Panel power, Molex KK-396 8-pin	Stern CN2 order: 1 −112V, 2 −100V, 3 key, 4–5 GND, 6 +5V, 7 +12V (via JP1), 8 +65V

Wire the isolated DC-DC output straight to NCH6100HV #2's input, off-board. Both float at −130 V.

⚠️ J2 pinout is a placeholder. It follows the Stern supply, not necessarily your WPC panel. Map it to your panel before you plug anything in.

Files

File	What
gen_kicad.py	Generates the schematic and the project's net classes from the PARTS table. The source of truth.
check_netlist.py	Exports the netlist with kicad-cli and checks every pin against PARTS
plasma_dmd_psu.kicad_sch	Generated schematic (labels-per-pin style: connectivity is by net label)
plasma_dmd_psu.pdf	Plot of the schematic

python hardware/kicad/gen_kicad.py
python hardware/kicad/check_netlist.py

Re-running gen_kicad.py overwrites the schematic. Either keep editing PARTS and regenerate, or stop using the generator once you start editing the schematic in KiCad.

Net classes (already in the project)

Class	Nets	Clearance	Track
HV	+90V_RAW, +65V, −130V_RAW, −112V, −100V, HVP/HVN_MOD and all regulator internals	1.3 mm (3.0 mm to LV via custom rules)	0.6 mm
Power	GND, +12V*, +5V, +12V_PANEL	0.3 mm	1.0 mm
Default	Watchdog signals, LED cathode/anode nodes	0.25 mm	0.4 mm

PCB (rev 0.1)

The board is 170 × 125 mm, 2 layers, with 4 × M3 holes. It is fully routed with a bottom-layer GND pour. DRC is clean: 0 violations, 0 unconnected pads, schematic parity OK.

• Left: low voltage. 12 V input, Mini560, ESP32 watchdog, relay, F1–F3.
• Right: high voltage. +65 V regulator at the top, −112/−100 V regulator at the bottom. A dashed silkscreen line marks the boundary, with DANGER text on both sides.
• J2 (panel) straddles the boundary. Its LV pins (GND, +5V, +12V) leave towards the left, its HV pins towards the right.
• Terminal blocks sit on the top and bottom edges, with wire entries facing outwards.
• Heatsink space is left above Q3, Q5 and Q6.

⚠️ The TO-220 tabs are live. Q3's tab is at +90 V, Q5's at −130 V and Q6's at Q6_C. Give each transistor its own heatsink, keep the heatsinks apart, and don't let them touch anything.

Clearance rules

The classes are in the project, and the custom rules are in plasma_dmd_psu.kicad_dru. Later rules win.

Between	Clearance	Why
HV and LV (GND, 12 V, 5 V, watchdog)	3.0 mm	Keeps HV well away from the touchable side
HV and HV	1.3 mm	IPC-2221 B2 needs 1.25 mm up to 300 V
HV and LV, next to a connector pin	1.8 mm	Fixed pin pitch of J2/J5/J7
HV and HV, next to a transistor pin	1.0 mm	TO-220 pin escape; same-polarity nets only
Pins inside one connector / transistor / HV electrolytic	0.75 / 0.6 / 2.5 mm	Fixed footprint pitch

Regenerating the board

The layout is produced by two scripts, run with KiCad's Python while KiCad is closed:

"C:/Users/patri/AppData/Local/Programs/KiCad/10.0/bin/python.exe" hardware/kicad/layout_pcb.py
"C:/Users/patri/AppData/Local/Programs/KiCad/10.0/bin/python.exe" hardware/kicad/route_pcb.py

• layout_pcb.py places every footprint from its PLACE table and draws the outline, holes and silkscreen. It also swaps in any footprint that changed in the schematic. It deletes all tracks and zones.
• route_pcb.py autoroutes with Freerouting (tools/freerouting/, needs Java 25):
  • It routes with oversized tracks and vias, then shrinks them to their real width. This turns the router's smaller clearances into 3 mm for HV to LV and 1.3 mm for HV to HV.
  • It adds fixed escape stubs on J2 and the GND pour.
  • Run DRC afterwards: kicad-cli pcb drc --schematic-parity --refill-zones hardware/kicad/plasma_dmd_psu.kicad_pcb.

Once you start hand-editing the board in KiCad, stop running these scripts. They would overwrite your edits.

Before ordering

• Check every footprint against the parts you actually buy: fuse holders, the 12.5 mm caps, the R13 5 W size, and the terminal block pitch.
• Map J2 to your panel's power connector. The current order follows the Stern CN2 connector.
• Check heatsink size and clearance for Q3/Q5/Q6.
• Consider conformal coating on the HV side.
• Get a second pair of eyes on the HV layout.

Verified so far

• The schematic loads in KiCad 10.0.6, and ERC reports 0 violations.
• check_netlist.py: all 122 pins sit on the intended nets (31 nets).
• PCB DRC with schematic parity: 0 violations, 0 unconnected pads.
• All symbols and footprints come from the KiCad 10 standard libraries.
• Transistor pinouts match the footprints: MJE15030/31 are B-C-E (TO-220); MPSA42/92 are E-B-C (TO-92); 2N7000 is S-G-D.

Not verified: the circuit itself on real hardware, and the module current ratings.