Add routed PSU carrier board layout (rev 0.1)

- Placement script (layout_pcb.py): LV left, HV right, panel connector on the
  boundary, terminal blocks on the edges, heatsink space for the TO-220s
- Freerouting-based routing script (route_pcb.py) that routes with oversized
  tracks/vias and shrinks them, giving 3 mm HV-to-LV and 1.3 mm HV-to-HV
- Custom DRC rules (plasma_dmd_psu.kicad_dru) with documented exceptions
- Wide TO-92 footprints; schematic generator now keeps symbol UUIDs
- DRC: 0 violations, 0 unconnected pads, schematic parity OK

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

.gitignore

@@ -17,3 +17,12 @@ __pycache__/
 # KiCad generated reports
 hardware/kicad/erc.rpt
 *.net
+
+# Local tools (Freerouting jar)
+tools/
+
+# KiCad local history
+.history/
+
+# Freerouting work files
+hardware/kicad/route/