This website requires JavaScript.
Explore
Help
Sign In
Quartus
/
cpu
Watch
1
Star
0
Fork
0
Code
Issues
Pull Requests
Actions
Packages
Projects
Releases
Wiki
Activity
1
Commit
1
Branch
0
Tags
01f6ecf396edd8d9790481ec17e316af3524d8de
T
Code
Clone
HTTPS
Tea CLI
Open with VS Code
Open with VSCodium
Open with Intellij IDEA
Download ZIP
Download TAR.GZ
Download BUNDLE
Patrick Valk
01f6ecf396
init.
2016-11-14 14:07:01 +01:00
.gitignore
init.
2016-11-14 14:07:01 +01:00
8bit_memory.bdf
init.
2016-11-14 14:07:01 +01:00
8bit_memory.bsf
init.
2016-11-14 14:07:01 +01:00
Clk.bdf
init.
2016-11-14 14:07:01 +01:00
Clk.bsf
init.
2016-11-14 14:07:01 +01:00
clockDevider.bsf
init.
2016-11-14 14:07:01 +01:00
clockDevider.v
init.
2016-11-14 14:07:01 +01:00
CPU_Main.bdf
init.
2016-11-14 14:07:01 +01:00
CPU.bdf
init.
2016-11-14 14:07:01 +01:00
CPU.qpf
init.
2016-11-14 14:07:01 +01:00
CPU.qsf
init.
2016-11-14 14:07:01 +01:00
CPU.qws
init.
2016-11-14 14:07:01 +01:00
Enabler2.bsf
init.
2016-11-14 14:07:01 +01:00
Enabler.bdf
init.
2016-11-14 14:07:01 +01:00
Enabler.bsf
init.
2016-11-14 14:07:01 +01:00
Memory Controller.bdf
init.
2016-11-14 14:07:01 +01:00
Memory Controller.bsf
init.
2016-11-14 14:07:01 +01:00
memory.bdf
init.
2016-11-14 14:07:01 +01:00
Memory.bsf
init.
2016-11-14 14:07:01 +01:00
ram1.bsf
init.
2016-11-14 14:07:01 +01:00
ram1.v
init.
2016-11-14 14:07:01 +01:00
S
Description
No description provided
49
KiB
Languages
Verilog
100%