Public Access
mangavalkandClaude Opus 5.5
ab3e6ad0ac
The datasheet numbers columns from 1 (Fig. 3: "row 1", "Last pixel (512 / 256)") and puts odd columns on TVID, so x = 0 (column 1) now goes to TVID and x = 1 to VID; the encoder had them swapped. README wiring now lists the J1/J2 pins and power rails from Table 1, the 5 V buffer, and a pull-down on ENABLE so the panel stays off while the ESP32 boots without VCLK. encodeRow() documents its T4/T5 margins. docs/README.md open items are regrouped into done, hardware checks and software work. main.cpp counts seconds, not frames. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
88 lines
4.4 KiB
Markdown
88 lines
4.4 KiB
Markdown
# Notes
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- Plan: https://claude.ai/code/artifact/3b9eda11-a87e-4eea-bbb9-e6454e558991
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- Datasheet: [datasheet/EL512.256-H3 FRB.pdf](datasheet/EL512.256-H3%20FRB.pdf)
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## Approach
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I2S0 in 8-bit parallel (LCD) mode with a circular DMA descriptor chain. Each DMA byte
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is one VCLK period:
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| Bit | Signal |
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|-----|--------|
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| 0 | VID (even columns) |
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| 1 | TVID (odd columns) |
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| 2 | HS |
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| 3 | VS |
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The I2S0 BCK output drives VCLK. ENABLE (GPIO 25) and _LOWPWR (GPIO 26) are plain GPIO.
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I2S0 setup (`EL512Panel::startI2S()`), following bitluni's ESP32Lib 8-bit mode:
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- Clock: PLL_D2_CLK 160 MHz / `clkm_div_num` 32, `tx_bck_div_num` 1 -> 5 MHz, one byte
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per BCK period.
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- `lcd_en`, `lcd_tx_wrx2_en`, `tx_bits_mod` 8, `tx_fifo_mod` 1, `tx_chan_mod` 1,
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`tx_right_first`. With this setup each 32-bit DMA word goes out as bytes 2, 3, 0, 1,
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so `encodeRow()` stores clock c at `c ^ 2`.
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- Stream bits 0..3 -> `I2S0O_DATA_OUT16_IDX` + n; BCK -> VCLK (`INVERT_VCLK` flips it).
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- 18 descriptors of up to 15 lines (4080 bytes) each, looped; `eof` set once per frame.
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## From the datasheet
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The datasheet is the source of truth for everything in this section and wins over any
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other doc, comment or the plan.
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- Two-bit parallel mode is selected by removing jumper 2 (DCONFIG) of pin strip PS1
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(Table 3; factory default has jumpers 1 and 2 fitted). Even columns on VID, odd
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columns on TVID, numbered from the left as seen by the viewer; 256 VCLKs per row.
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The datasheet numbers from 1 (Fig. 3: "row 1", "Last pixel (512 / 256)"), so the
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leftmost pixel, x = 0 in the code, is column 1 and goes on TVID.
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- VCLK is active on the rising edge and should be kept running.
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- HS envelopes the pixels of a row: the visible pixels are the last 512 (two-bit mode:
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last 256 clocks) before HS falls. The number of VCLKs during HS high should be even.
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- The topmost row is the first HS high time ending after the rising edge of VS. Only
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the rising edge of VS is used; VS high/low time is at least 1 VCLK (T2).
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- Table 5: front porch T1 >= 100 µs, HS setup to VS T4 >= 1 VCLK, HS hold from VS
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T5 >= 3 µs, HS low T6 >= 4 VCLK, HS period T8 >= 50 µs, VS 70 Hz typ / 75 Hz max.
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- Figure 4 / Table 6: VID, TVID, HS and VS need 8 ns setup and 8 ns hold around the
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rising VCLK edge; VCLK period >= 33 ns (30 MHz max).
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- Inputs are HCT compatible with pull-ups (Table 4: high >= 2 V, low <= 0.8 V,
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abs. max Vcc1 + 0.5 V). ENABLE and _LOWPWR are on J2 and pulled high internally.
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## Open items
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Done:
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- [x] Implement `EL512Panel::startI2S()` (I2S0 LCD mode, 5 MHz from PLL_D2 / 32,
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GPIO matrix routing, circular `lldesc_t` chain).
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- [x] Handle the 8-bit LCD-mode byte-pair swap in `encodeRow()` (clock c at `c ^ 2`).
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- [x] Map x = 0 (datasheet column 1, odd) to TVID, not VID.
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Hardware checks (need the panel and a scope or logic analyser):
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- [ ] Self test first (Table 3): remove PS1 jumper 1, power up; all pixels except the
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first half of the top row should light. Refit jumper 1, remove jumper 2.
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- [ ] Scope: VCLK 5 MHz on GPIO 18; HS 256 clocks high / 16 low (54.4 µs, T6-T8);
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VS one line high per 14.2 ms frame (70.4 Hz); data changing on the falling VCLK
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edge with >= 8 ns setup/hold (Table 6); T1 220.8 µs, T4/T5 as in `encodeRow()`.
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If data changes on the rising edge, set `INVERT_VCLK`.
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- [ ] Confirm the I2S0 data signal base (`I2S0O_DATA_OUT16_IDX`): if GPIO 19/21/22/23
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stay idle, try `I2S0O_DATA_OUT8_IDX`.
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- [ ] Confirm the `^ 2` byte order. HS edges sit on word boundaries, so a wrong order
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does not show on HS; on the panel it shuffles pixels in groups of 8 (a 1-pixel
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line at x = 0 lands at x = 4).
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- [ ] Confirm the column parity: the checkerboard in `main.cpp` must look identical to
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the framebuffer, and the left border must sit on the panel's first column.
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- [ ] Add the 5 V buffer (74HCT245/74AHCT541) and a pull-down on ENABLE so the panel
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stays off while the ESP32 boots without VCLK (Table 1: ENABLE pulled high
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internally; Table 5 note 3: VCLK should be kept running).
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Software:
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- [ ] Tear-free updates: `show()` rewrites the stream while DMA reads it. Encode into
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a second buffer and swap descriptors at the per-frame EOF, or encode only during
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vertical blanking.
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- [ ] Unit test for `encodeRow()` (see `test/README`).
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- [ ] The 71 KB stream is one contiguous DMA allocation; with Wi-Fi on it may not fit.
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Fallback: per-line buffers or a line ring refilled from the EOF interrupt.
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