Public Access
mangavalkandClaude Opus 5.5
37d5bcc1f8
The datasheet (docs/datasheet, Planar 020-0354-00A) is now stated as the source of truth. Two-bit mode is PS1 jumper 2 (DCONFIG) removed (Table 3), not a generic "mode jumper". The README timing table now lists the Table 5/6 limits beside our values, and the notes add T1-T8, the 8 ns setup/hold from Figure 4 and the input levels from Table 4. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
63 lines
3.0 KiB
Markdown
63 lines
3.0 KiB
Markdown
# Notes
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- Plan: https://claude.ai/code/artifact/3b9eda11-a87e-4eea-bbb9-e6454e558991
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- Datasheet: [datasheet/EL512.256-H3 FRB.pdf](datasheet/EL512.256-H3%20FRB.pdf)
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## Approach
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I2S0 in 8-bit parallel (LCD) mode with a circular DMA descriptor chain. Each DMA byte
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is one VCLK period:
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| Bit | Signal |
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|-----|--------|
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| 0 | VID (even columns) |
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| 1 | TVID (odd columns) |
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| 2 | HS |
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| 3 | VS |
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The I2S0 BCK output drives VCLK. ENABLE (GPIO 25) and _LOWPWR (GPIO 26) are plain GPIO.
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I2S0 setup (`EL512Panel::startI2S()`), following bitluni's ESP32Lib 8-bit mode:
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- Clock: PLL_D2_CLK 160 MHz / `clkm_div_num` 32, `tx_bck_div_num` 1 -> 5 MHz, one byte
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per BCK period.
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- `lcd_en`, `lcd_tx_wrx2_en`, `tx_bits_mod` 8, `tx_fifo_mod` 1, `tx_chan_mod` 1,
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`tx_right_first`. With this setup each 32-bit DMA word goes out as bytes 2, 3, 0, 1,
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so `encodeRow()` stores clock c at `c ^ 2`.
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- Stream bits 0..3 -> `I2S0O_DATA_OUT16_IDX` + n; BCK -> VCLK (`INVERT_VCLK` flips it).
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- 18 descriptors of up to 15 lines (4080 bytes) each, looped; `eof` set once per frame.
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## From the datasheet
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The datasheet is the source of truth for everything in this section and wins over any
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other doc, comment or the plan.
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- Two-bit parallel mode is selected by removing jumper 2 (DCONFIG) of pin strip PS1
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(Table 3; factory default has jumpers 1 and 2 fitted). Even columns on VID, odd
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columns on TVID, numbered from the left as seen by the viewer; 256 VCLKs per row.
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- VCLK is active on the rising edge and should be kept running.
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- HS envelopes the pixels of a row: the visible pixels are the last 512 (two-bit mode:
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last 256 clocks) before HS falls. The number of VCLKs during HS high should be even.
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- The topmost row is the first HS high time ending after the rising edge of VS. Only
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the rising edge of VS is used; VS high/low time is at least 1 VCLK (T2).
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- Table 5: front porch T1 >= 100 µs, HS setup to VS T4 >= 1 VCLK, HS hold from VS
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T5 >= 3 µs, HS low T6 >= 4 VCLK, HS period T8 >= 50 µs, VS 70 Hz typ / 75 Hz max.
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- Figure 4 / Table 6: VID, TVID, HS and VS need 8 ns setup and 8 ns hold around the
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rising VCLK edge; VCLK period >= 33 ns (30 MHz max).
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- Inputs are HCT compatible with pull-ups (Table 4: high >= 2 V, low <= 0.8 V,
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abs. max Vcc1 + 0.5 V). ENABLE and _LOWPWR are on J2 and pulled high internally.
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## Open items
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- [x] Implement `EL512Panel::startI2S()` (I2S0 LCD mode, clock dividers for 5 MHz,
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GPIO matrix routing, circular `lldesc_t` chain).
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- [x] Handle the 8-bit LCD-mode byte-pair swap in `encodeRow()`.
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- [ ] Check on a scope: VCLK is 5 MHz on GPIO 18, HS is 256 clocks high / 16 low
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(54.4 us period), VS is one line high per 14.2 ms frame, data changes on the
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falling VCLK edge, VS/HS setup and hold (T4/T5). Unconfirmed until then: the
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DATA_OUT16 base and the `^ 2` byte order. HS edges sit on word boundaries, so a
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wrong order does not show on HS; on the panel it shuffles pixels in groups of 8
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(a 1-pixel line at x = 0 lands at x = 4).
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- [ ] Tear-free updates (double buffer or swap at VS).
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- [ ] Unit test for `encodeRow()`.
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