Invert VCLK to fix pixel jitter

Uninverted, the rising BCK edge landed on the boundary between byte pairs,
so the panel sampled data mid-change and the image jittered. Inverted, the
edge sits mid-pair; verified stable on the panel. Also note the row-stripe
brightness drift as an open item.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

docs/README.md

@@ -73,9 +73,11 @@ Hardware checks:
 - [ ] HS reads ~18,030 Hz on PCNT where 5 MHz / 272 = 18,382 Hz is expected (~2% low)
       while VCLK reads 5.0 MHz. Frame rate is still ~70 Hz; cause unknown, check on a
       scope (HS 256 clocks high / 16 low, T6-T8).
-- [ ] Scope: data changing away from the rising VCLK edge with >= 8 ns setup/hold
+- [x] VCLK edge phase: with `INVERT_VCLK = false` the image jittered (rising edge on
-      (Table 6); which BCK edge lines up with the byte-pair boundary is unverified. If
+      the byte-pair boundary); `true` puts it mid-pair and the jitter is gone.
-      pixels look shifted or noisy, set `INVERT_VCLK`.
+- [ ] "row stripes" test image: brightness drifts in slow waves. Unexplained;
+      suspected beat between the alternating full/empty row load and the panel's
+      DC/DC converter or row drive.
 - [ ] Confirm the `^ 2` byte order. HS edges sit on word boundaries, so a wrong order
       does not show on HS; on the panel it shuffles pixels in groups of 8 (a 1-pixel
       line at x = 0 lands at x = 4).

lib/EL512/src/EL512Panel.cpp

@@ -23,9 +23,10 @@ static_assert(I2S_CLKM_DIV >= 2 && I2S_CLKM_DIV <= 255, "clkm_div_num out of ran
 constexpr uint32_t I2S0_DATA_SIGNAL_BASE = I2S0O_DATA_OUT16_IDX;
 
 // BCK runs at half the byte rate (measured: 2.5 MHz BCK at 5 MHz bytes), so each
-// VCLK period spans two identical bytes. Unverified which BCK edge lines up with
+// VCLK period spans two identical bytes. Uninverted, the rising edge landed on the
-// the byte pair boundary: if pixels look shifted or noisy, set this to true.
+// byte-pair boundary and the image jittered; inverted, it sits mid-pair (verified
-constexpr bool INVERT_VCLK = false;
+// on the panel).
+constexpr bool INVERT_VCLK = true;
 
 // One DMA descriptor per stream chunk (descriptor limit 4095 bytes).
 static_assert(EL512Panel::LINES_PER_CHUNK * EL512Panel::ROW_BYTES <= 4092, "descriptor too long");