Invert VCLK to fix pixel jitter

Uninverted, the rising BCK edge landed on the boundary between byte pairs,
so the panel sampled data mid-change and the image jittered. Inverted, the
edge sits mid-pair; verified stable on the panel. Also note the row-stripe
brightness drift as an open item.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
This commit is contained in:
mangavalkandClaude Opus 5.5 committed 2026-10-18 18:54:25 +02:00
1 parent df78b5e72c
commit 901a213079
2 files changed
+9 -6

No files matched your search

+4 -3
View File
@@ -23,9 +23,10 @@ static_assert(I2S_CLKM_DIV >= 2 && I2S_CLKM_DIV <= 255, "clkm_div_num out of ran
constexpr uint32_t I2S0_DATA_SIGNAL_BASE = I2S0O_DATA_OUT16_IDX;
// BCK runs at half the byte rate (measured: 2.5 MHz BCK at 5 MHz bytes), so each
// VCLK period spans two identical bytes. Unverified which BCK edge lines up with
// the byte pair boundary: if pixels look shifted or noisy, set this to true.
constexpr bool INVERT_VCLK = false;
// VCLK period spans two identical bytes. Uninverted, the rising edge landed on the
// byte-pair boundary and the image jittered; inverted, it sits mid-pair (verified
// on the panel).
constexpr bool INVERT_VCLK = true;
// One DMA descriptor per stream chunk (descriptor limit 4095 bytes).
static_assert(EL512Panel::LINES_PER_CHUNK * EL512Panel::ROW_BYTES <= 4092, "descriptor too long");