Invert VCLK to fix pixel jitter

Uninverted, the rising BCK edge landed on the boundary between byte pairs,
so the panel sampled data mid-change and the image jittered. Inverted, the
edge sits mid-pair; verified stable on the panel. Also note the row-stripe
brightness drift as an open item.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

docs/README.md

@@ -73,9 +73,11 @@ Hardware checks:
 - [ ] HS reads ~18,030 Hz on PCNT where 5 MHz / 272 = 18,382 Hz is expected (~2% low)
       while VCLK reads 5.0 MHz. Frame rate is still ~70 Hz; cause unknown, check on a
       scope (HS 256 clocks high / 16 low, T6-T8).
-- [ ] Scope: data changing away from the rising VCLK edge with >= 8 ns setup/hold
-      (Table 6); which BCK edge lines up with the byte-pair boundary is unverified. If
-      pixels look shifted or noisy, set `INVERT_VCLK`.
+- [x] VCLK edge phase: with `INVERT_VCLK = false` the image jittered (rising edge on
+      the byte-pair boundary); `true` puts it mid-pair and the jitter is gone.
+- [ ] "row stripes" test image: brightness drifts in slow waves. Unexplained;
+      suspected beat between the alternating full/empty row load and the panel's
+      DC/DC converter or row drive.
 - [ ] Confirm the `^ 2` byte order. HS edges sit on word boundaries, so a wrong order
       does not show on HS; on the panel it shuffles pixels in groups of 8 (a 1-pixel
       line at x = 0 lands at x = 4).