mangavalkandClaude Opus 5.5
dbc1f0041f
- Design docs: 12 V DC power supply, safety and bring-up, ESP32 interface, BOM - PSU schematic (schemdraw) and KiCad 10 carrier-board project with HV net classes - ESP32 PlatformIO firmware skeleton with HV watchdog toggle - Reference schematic of the Stern 520-5138-00 display PSU Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
36 lines
1.3 KiB
Markdown
36 lines
1.3 KiB
Markdown
# ESP32 interface
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Board: **Wemos D1 mini ESP32**, powered from the 5 V rail.
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## Level shifting
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The panel inputs are 5 V TTL and the ESP32 is 3.3 V. Use a **74HCT245** (HCT only, because it accepts 3.3 V
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inputs) powered from 5 V, with DIR tied high (A→B) and OE tied low.
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## Pin plan
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| Signal (to panel, through 74HCT245) | GPIO | Notes |
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|---|---|---|
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| Dot clock | 18 | VSPI SCK |
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| Serial dot data | 23 | VSPI MOSI |
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| Column latch | 17 | |
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| Row data | 16 | |
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| Row clock | 26 | |
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| Display enable | 22 | Pull to *off* state at the 245 input |
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| HV watchdog toggle | 21 | Charge pump → relay (see safety.md) |
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| +65 V monitor (optional) | 34 | ADC, 2 × 1 MΩ + 33 kΩ divider |
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The strapping pins (0, 2, 5, 12, 15) are avoided so nothing twitches during boot.
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## Panel data connector
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- [ ] Map the panel's 14-pin data connector (signal ↔ pin) for this specific panel before wiring.
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## Scanning
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- 128 columns × 32 rows, about 120 Hz frame rate (as on WPC).
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- Per row: shift 128 bits of dot data (SPI), latch the columns, advance the row (row data is high
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for the first row only, then clock the row once per row).
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- The panel must never sit with one row lit. Scanning runs continuously, and the HV watchdog is
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toggled once per scanned row (about 2 kHz, so the charge pump stays charged).
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