mangavalkandClaude Opus 5.5
cdf24e0b4b
- PCB rev 0.1: Power3A class (1.5 mm) for the 12 V input path, Aavid clip-on heatsinks on Q3/Q5/Q6 (project footprint library), T-junction healing and via shrink in the router; DRC 0 errors - Current-capacity and heatsink documentation - CLAUDE.md with project decisions, workflow and gotchas - docs/design-review.md: review of a module-only PSU (rev 0.2) and cost estimate - Project paused for budget and safety reasons Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
157 lines
8.2 KiB
Markdown
157 lines
8.2 KiB
Markdown
# KiCad project: PSU carrier board
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Open `plasma_dmd_psu.kicad_pro` in KiCad 10.
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The board carries the fuses, the HV watchdog, both regulators (copied from Stern 520-5138-00) and
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the connectors. The AliExpress modules sit **off-board** and connect through Phoenix 5.08 mm screw terminals:
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| Connector | Goes to | Pins |
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|---|---|---|
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| J1 | 12 V DC brick | +12V, GND |
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| J3 | Mini560 5 V buck | IN+, IN−, OUT+, OUT− |
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| J4 | Relay module | VCC, GND, IN, COM, NO |
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| J5 | NCH6100HV #1 (set 90 V) | VIN, GND, HV+ |
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| J6 | Isolated DC-DC input | VIN, GND |
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| J7 | NCH6100HV #2 (set 130 V) output | HV+ (→ GND), GND (→ −130 V raw) |
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| J8 | ESP32 | 5V, GND, GPIO21 (watchdog) |
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| J2 | Panel power, Molex KK-396 8-pin | Stern CN2 order: 1 −112V, 2 −100V, 3 key, 4–5 GND, 6 +5V, 7 +12V (via JP1), 8 +65V |
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Wire the isolated DC-DC output straight to NCH6100HV #2's input, off-board. Both float at −130 V.
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> ⚠️ **J2 pinout is a placeholder.** It follows the Stern supply, not necessarily your WPC panel.
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> Map it to your panel before you plug anything in.
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## Files
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| File | What |
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|---|---|
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| `gen_kicad.py` | Generates the schematic and the project's net classes from the `PARTS` table. **The source of truth.** |
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| `check_netlist.py` | Exports the netlist with kicad-cli and checks every pin against `PARTS` |
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| `plasma_dmd_psu.kicad_sch` | Generated schematic (labels-per-pin style: connectivity is by net label) |
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| `plasma_dmd_psu.pdf` | Plot of the schematic |
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| `plasma_dmd.pretty/`, `fp-lib-table` | Project footprint library (courtyard-less heatsink) |
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| `layout_pcb.py`, `route_pcb.py` | Placement and autorouting scripts (see below) |
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| `plasma_dmd_psu.kicad_dru` | Custom clearance rules |
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```bash
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python hardware/kicad/gen_kicad.py
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python hardware/kicad/check_netlist.py
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```
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Re-running `gen_kicad.py` **overwrites the schematic**. Either keep editing `PARTS` and regenerate, or
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stop using the generator once you start editing the schematic in KiCad.
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## Net classes (already in the project)
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| Class | Nets | Clearance | Track |
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|---|---|---|---|
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| HV | +90V_RAW, +65V, −130V_RAW, −112V, −100V, HVP/HVN_MOD and all regulator internals | 1.3 mm (3.0 mm to LV via custom rules) | 0.6 mm |
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| Power3A | +12V_IN, +12V (behind the 3 A fuse F1) | 0.3 mm | 1.5 mm |
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| Power | GND (plus the bottom pour), +12V_HV/HVP/HVN, +5V, +12V_PANEL | 0.3 mm | 1.0 mm |
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| Default | Watchdog signals, LED cathode/anode nodes | 0.25 mm | 0.4 mm |
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## PCB (rev 0.1)
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The board is 170 × 125 mm, 2 layers, with 4 × M3 holes. It is fully routed with a bottom-layer GND pour.
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DRC is clean: 0 violations, 0 unconnected pads, schematic parity OK.
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- **Left: low voltage.** 12 V input, Mini560, ESP32 watchdog, relay, F1–F3.
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- **Right: high voltage.** +65 V regulator at the top, −112/−100 V regulator at the bottom.
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A dashed silkscreen line marks the boundary, with DANGER text on both sides.
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- **J2 (panel)** straddles the boundary. Its LV pins (GND, +5V, +12V) leave towards the left, its HV pins towards the right.
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- **Terminal blocks** sit on the top and bottom edges, with wire entries facing outwards.
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- **Heatsinks** HS1–HS3 (Aavid 576802B03900G clip-on, about 20 K/W) sit on Q3, Q5 and Q6.
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> ⚠️ **The heatsinks are live.** Each one clips straight onto its transistor's tab: HS1 is at +90 V,
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> HS2 at −130 V and HS3 at Q6_C. That's why each heatsink's solder pin is on the collector net,
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> so the HV clearance rules also protect it. Never let the heatsinks touch each other or anything else.
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### Heatsinks
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- **Footprint:** `plasma_dmd:Heatsink_AAVID_576802B03900G_NoCourtyard` in the project library
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`plasma_dmd.pretty`. It's a copy of KiCad's footprint with the courtyard and silkscreen outline
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removed, because the clip wraps around the transistor and would always overlap its courtyard.
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The outline is kept on F.Fab, and the footprint is marked "exempt from courtyard requirement".
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- **Placement:** `layout_pcb.py` places each heatsink relative to its transistor (`heatsink_for()`),
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with its tab face on the TO-220 tab.
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- **Dissipation (estimate):** about 1–1.5 W per transistor. Bare TO-220 runs at about 62 K/W
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(60–90 °C rise); with the heatsink, about 20 K/W (about 30 °C rise).
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- **Project setting:** "PTH inside courtyard" is set to ignore, because each heatsink pin sits just
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behind its tab, inside the transistor courtyard. Courtyard *overlaps* are still checked for all
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other parts.
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- **Remaining DRC items:** the 9 silkscreen warnings are the TO-220 outlines over the heatsink pins.
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The fab clips silkscreen off pads, so they're harmless.
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### Current capacity
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Track widths follow IPC-2221 for 1 oz outer copper. Currents are estimated from the fuses.
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| Net | Max current (fuse) | Width | Capacity at 10 °C rise |
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|---|---|---|---|
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| +12V_IN, +12V | 3 A (F1) | 1.5 mm | ≈ 3.2 A |
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| GND return | 3 A | 1.0 mm + solid bottom pour on the LV side | well above 3 A |
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| +12V_HV | 2 A (F2 + F3) | 1.0 mm | ≈ 2.4 A |
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| +12V_HVP, +12V_HVN | 1 A (F2, F3) | 1.0 mm | ≈ 2.4 A |
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| +5V | about 1 A (unfused, from the Mini560) | 1.0 mm | ≈ 2.4 A |
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| HV nets | 100 mA (F4, F5) | 0.6 mm | ≈ 1.7 A (width set by clearance, not current) |
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| Signals | mA | 0.4 mm | ≈ 1.2 A |
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The 12 V input path, GND and +5V have no vias.
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- **Note on F3:** if the negative rail ever drew the full 100 mA that F5 allows (about 13 W), the
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isolated converter plus the boost module would pull more than 1 A at 12 V. That would blow F3.
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Measure the real HV current at bring-up.
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- **Note on +5V:** the 5 V side isn't fused on its own. Consider a polyfuse (about 1.5 A) if the panel
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or the ESP32 wiring could short.
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### Clearance rules
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The classes are in the project, and the custom rules are in `plasma_dmd_psu.kicad_dru`. Later rules win.
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| Between | Clearance | Why |
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| HV and LV (GND, 12 V, 5 V, watchdog) | **3.0 mm** | Keeps HV well away from the touchable side |
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| HV and HV | 1.3 mm | IPC-2221 B2 needs 1.25 mm up to 300 V |
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| HV and LV, next to a connector pin | 1.8 mm | Fixed pin pitch of J2/J5/J7 |
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| HV and HV, next to a transistor pin | 1.0 mm | TO-220 pin escape; same-polarity nets only |
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| Pins inside one connector / transistor / HV electrolytic | 0.75 / 0.6 / 2.5 mm | Fixed footprint pitch |
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### Regenerating the board
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The layout is produced by two scripts, run with KiCad's Python while KiCad is closed:
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```bash
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"C:/Users/patri/AppData/Local/Programs/KiCad/10.0/bin/python.exe" hardware/kicad/layout_pcb.py
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"C:/Users/patri/AppData/Local/Programs/KiCad/10.0/bin/python.exe" hardware/kicad/route_pcb.py
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```
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- `layout_pcb.py` places every footprint from its `PLACE` table and draws the outline, holes and silkscreen.
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It also swaps in any footprint that changed in the schematic. **It deletes all tracks and zones.**
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- `route_pcb.py` autoroutes with Freerouting (`tools/freerouting/`, needs Java 25):
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- It routes with oversized tracks and vias, then shrinks them to their real width. This turns
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the router's smaller clearances into 3 mm for HV to LV and 1.3 mm for HV to HV.
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- It adds fixed escape stubs on J2 and the GND pour.
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- Run DRC afterwards: `kicad-cli pcb drc --schematic-parity --refill-zones hardware/kicad/plasma_dmd_psu.kicad_pcb`.
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Once you start hand-editing the board in KiCad, stop running these scripts. They would overwrite your edits.
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### Before ordering
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- [ ] Check every footprint against the parts you actually buy: fuse holders, the 12.5 mm caps, the R13 5 W size, and the terminal block pitch.
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- [ ] Map J2 to your panel's power connector. The current order follows the Stern CN2 connector.
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- [ ] Check the heatsink orientation against the Aavid 5768 drawing. KiCad has no 3D model for it, so it isn't visible in the render.
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- [ ] Consider conformal coating on the HV side.
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- [ ] Get a second pair of eyes on the HV layout.
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## Verified so far
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- The schematic loads in KiCad 10.0.6, and ERC reports 0 violations.
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- `check_netlist.py`: all 122 pins sit on the intended nets (31 nets).
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- PCB DRC with schematic parity: 0 violations, 0 unconnected pads.
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- All symbols and footprints come from the KiCad 10 standard libraries.
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- Transistor pinouts match the footprints: MJE15030/31 are B-C-E (TO-220); MPSA42/92 are E-B-C (TO-92); 2N7000 is S-G-D.
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**Not verified:** the circuit itself on real hardware, and the module current ratings.
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