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28c666506ef07f84c1c57ad326f182c9fb7593b0
Plasma-DMD/hardware/kicad/plasma_dmd_psu.kicad_sch
T
mangavalkandClaude Opus 5.5 28c666506e Add routed PSU carrier board layout (rev 0.1) 
- Placement script (layout_pcb.py): LV left, HV right, panel connector on the
  boundary, terminal blocks on the edges, heatsink space for the TO-220s
- Freerouting-based routing script (route_pcb.py) that routes with oversized
  tracks/vias and shrinks them, giving 3 mm HV-to-LV and 1.3 mm HV-to-HV
- Custom DRC rules (plasma_dmd_psu.kicad_dru) with documented exceptions
- Wide TO-92 footprints; schematic generator now keeps symbol UUIDs
- DRC: 0 violations, 0 unconnected pads, schematic parity OK

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-24 02:58:35 +02:00

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(wire (pts (xy 33.02 373.38) (xy 30.48 373.38)) (stroke (width 0) (type default)) (uuid "5a568500-5ba6-409f-aaed-0651c1c96212"))
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(wire (pts (xy 33.02 375.92) (xy 30.48 375.92)) (stroke (width 0) (type default)) (uuid "957a0a03-5e5c-4123-9f06-1a95f9651af7"))
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(wire (pts (xy 33.02 378.46) (xy 30.48 378.46)) (stroke (width 0) (type default)) (uuid "6cb76165-fdb5-4e49-a4ef-0a1a3778173f"))
(label "+12V_PANEL" (at 30.48 378.46 180) (fields_autoplaced yes) (effects (font (size 1.27 1.27)) (justify right bottom)) (uuid "e195b1d3-d254-493e-8680-5e648eb8e48a"))
(wire (pts (xy 33.02 381.0) (xy 30.48 381.0)) (stroke (width 0) (type default)) (uuid "2b6eac02-f288-46e8-8fec-abca1102de1a"))
(label "+65V" (at 30.48 381.0 180) (fields_autoplaced yes) (effects (font (size 1.27 1.27)) (justify right bottom)) (uuid "6b3248b5-b66c-433b-b313-ceb16d122d54"))
(symbol (lib_id "Connector_Generic:Conn_01x02") (at 88.9 370.84 0) (unit 1)
(exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid "0421b83c-1e44-4b8e-a712-c8ed64e80171")
(property "Reference" "JP1" (at 93.98 369.57 0) (effects (font (size 1.27 1.27)) (justify left)))
(property "Value" "Fit if panel uses +12V" (at 93.98 372.11 0) (effects (font (size 1.27 1.27)) (justify left)))
(property "Footprint" "Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical" (at 88.9 370.84 0) (effects (font (size 1.27 1.27)) (hide yes)))
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(pin "1" (uuid "82fb07d5-a464-4424-931e-577f9f3f717c"))
(pin "2" (uuid "338212f6-9288-47e7-af97-2739ddcd4497"))
(instances (project "plasma_dmd_psu" (path "/d8fec46f-dde9-4522-8610-66699deb1f29" (reference "JP1") (unit 1))))
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(wire (pts (xy 83.82 370.84) (xy 81.28 370.84)) (stroke (width 0) (type default)) (uuid "281dfd15-bacb-4ff1-a37e-2861471a6196"))
(label "+12V" (at 81.28 370.84 180) (fields_autoplaced yes) (effects (font (size 1.27 1.27)) (justify right bottom)) (uuid "01ff64d5-4f12-44d3-a1f4-622534db4aa8"))
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(symbol (lib_id "Mechanical:MountingHole") (at 139.7 370.84 0) (unit 1)
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(exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid "16e16879-49c4-4a5e-8c7e-e75d11458984")
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(text "1. 12 V input and +5 V (Mini560 off-board)" (exclude_from_sim no) (at 25.4 33.02 0) (effects (font (size 2.54 2.54) (bold yes)) (justify left bottom)) (uuid "696f9e14-8950-4bfd-b3e5-c947d0f982ef"))
(text "2. HV enable relay + hardware watchdog (relay module off-board)" (exclude_from_sim no) (at 25.4 86.36000000000001 0) (effects (font (size 2.54 2.54) (bold yes)) (justify left bottom)) (uuid "1cfaece6-d6b8-4eb7-806a-de537e0accbf"))
(text "3. Positive HV: NCH6100HV #1 off-board + original regulator -> +65 V" (exclude_from_sim no) (at 25.4 167.64000000000001 0) (effects (font (size 2.54 2.54) (bold yes)) (justify left bottom)) (uuid "e6a6861f-5483-4196-a906-f0239d886493"))
(text "4. Negative HV: isolated DC-DC + NCH6100HV #2 off-board (FLOATING at -130 V) + regulator -> -112 / -100 V" (exclude_from_sim no) (at 25.4 248.92000000000002 0) (effects (font (size 2.54 2.54) (bold yes)) (justify left bottom)) (uuid "0f20b32e-cf4a-44ed-93fc-23456462caa1"))
(text "5. Panel connector and mounting" (exclude_from_sim no) (at 25.4 358.14000000000004 0) (effects (font (size 2.54 2.54) (bold yes)) (justify left bottom)) (uuid "3e6a265e-fa13-4c77-a6a8-ab8dabe9ecc4"))
(text "Plasma DMD - 12 V DC PSU carrier board (rev 0.1, unverified)\nConnectivity is by net labels: every pin has a stub + label. Off-board modules connect via J3-J7.\nPanel voltages are set by zeners D5 (68 V -> about +65 V) and D7+D8 (113 V -> about -112 / -100 V), copied from Stern 520-5138-00.\nSAFETY: keep >= 3 mm clearance (more is better) between HV nets (+90V_RAW, +65V, -130V_RAW, -112V, -100V, HVN_MOD, HVP_MOD) and low-voltage nets.\nJ2 pin order follows the Stern CN2 connector: map it to YOUR panel before use. Pin 3 is the key position." (exclude_from_sim no) (at 25.4 12.7 0) (effects (font (size 1.778 1.778)) (justify left top)) (uuid "2e69a240-2cb4-4ff7-b393-745da68f3c08"))
(sheet_instances (path "/" (page "1")))
)
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