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28c666506ef07f84c1c57ad326f182c9fb7593b0
Plasma-DMD/hardware/kicad/plasma_dmd_psu.kicad_pcb
T
mangavalkandClaude Opus 5.5 28c666506e Add routed PSU carrier board layout (rev 0.1) 
- Placement script (layout_pcb.py): LV left, HV right, panel connector on the
  boundary, terminal blocks on the edges, heatsink space for the TO-220s
- Freerouting-based routing script (route_pcb.py) that routes with oversized
  tracks/vias and shrinks them, giving 3 mm HV-to-LV and 1.3 mm HV-to-HV
- Custom DRC rules (plasma_dmd_psu.kicad_dru) with documented exceptions
- Wide TO-92 footprints; schematic generator now keeps symbol UUIDs
- DRC: 0 violations, 0 unconnected pads, schematic parity OK

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-24 02:58:35 +02:00

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(allow_soldermask_bridges_in_footprints no)
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