Heatsinks, wider 12 V tracks, design review; pause project
- PCB rev 0.1: Power3A class (1.5 mm) for the 12 V input path, Aavid clip-on heatsinks on Q3/Q5/Q6 (project footprint library), T-junction healing and via shrink in the router; DRC 0 errors - Current-capacity and heatsink documentation - CLAUDE.md with project decisions, workflow and gotchas - docs/design-review.md: review of a module-only PSU (rev 0.2) and cost estimate - Project paused for budget and safety reasons Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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@@ -112,7 +112,7 @@
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"nonmirrored_text_on_back_layer": "warning",
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"npth_inside_courtyard": "error",
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"padstack": "warning",
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"pth_inside_courtyard": "error",
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"pth_inside_courtyard": "ignore",
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"shorting_items": "error",
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"silk_edge_clearance": "warning",
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"silk_over_copper": "warning",
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@@ -542,13 +542,32 @@
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"microvia_drill": 0.1,
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"name": "Power",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"priority": 1,
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"priority": 2,
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"track_width": 1.0,
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"tuning_profile": "",
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"via_diameter": 1.0,
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"via_drill": 0.5,
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"wire_width": 6
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},
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{
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"bus_width": 12,
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"clearance": 0.3,
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"diff_pair_gap": 0.25,
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"diff_pair_via_gap": 0.25,
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"diff_pair_width": 0.2,
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"line_style": 0,
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"microvia_diameter": 0.3,
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"microvia_drill": 0.1,
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"name": "Power3A",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"priority": 1,
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"track_width": 1.5,
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"tuning_profile": "",
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"via_diameter": 1.0,
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"via_drill": 0.5,
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"wire_width": 6
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}
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],
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"meta": {
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@@ -622,17 +641,17 @@
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"pattern": "/Q6_C"
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},
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{
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"netclass": "Power",
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"pattern": "/GND"
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},
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{
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"netclass": "Power",
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"netclass": "Power3A",
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"pattern": "/+12V"
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},
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{
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"netclass": "Power",
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"netclass": "Power3A",
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"pattern": "/+12V_IN"
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},
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{
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"netclass": "Power",
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"pattern": "/GND"
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},
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{
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"netclass": "Power",
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"pattern": "/+12V_HV"
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