diff --git a/CLAUDE.md b/CLAUDE.md new file mode 100644 index 0000000..87fd8d9 --- /dev/null +++ b/CLAUDE.md @@ -0,0 +1,72 @@ +# Plasma DMD — notes for Claude + +The goal: drive a second-hand 128×32 pinball **plasma** DMD panel standalone from a **Wemos D1 mini ESP32**, +powered from **12 V DC only**. The panel was originally on a Williams WPC controller and was bought on +2021-09-18 for €37. No original controller or PSU came with it. + +## Status (keep this section up to date) + +- **PAUSED (2026-10-24)** at the user's request, because of the cost and the safety risk. If resuming, consider the + cheaper, no-high-voltage alternative discussed: a 128×32 HUB75 LED matrix driven by the same ESP32 (about €30–50). + +- Design docs in `docs/`, PSU schematic and routed PCB rev 0.1 in `hardware/kicad/`, firmware skeleton in `firmware/`. +- Not yet known: the panel's make and part number, its power and data connector pinouts, and the + polarity of its control signals. **J2's pinout is a placeholder (Stern CN2 order).** +- Nothing is built or tested on real hardware. +- **Proposed rev 0.2: module-only PSU** (no linear regulators or heatsinks), reviewed in `docs/design-review.md`. + It's waiting on the must-fix items M1–M4 there. The schematic and PCB are still rev 0.1. + +## Design decisions (don't silently change these) + +- **PSU:** + - A 12 V brick feeds a Mini560 (5 V) and two NCH6100HV boost modules: one at 90 V, and one at + 130 V fed through an isolated DC-DC, so its output floats and becomes −130 V. + - Those raw rails feed a copy of the regulator section of the Stern 520-5138-00 (zener-referenced + followers), giving about +65 V, −112 V and −100 V. + - The zeners set the panel voltages, not the module trim pots. +- **Modules sit off-board** on screw terminals. The PCB is a carrier board. +- **Safety first:** + - A relay switches the 12 V feed to the HV modules. + - The relay is driven by a hardware charge-pump watchdog, toggled by GPIO21 once per scanned row + (about 2 kHz). If toggling stops, the HV drops. + - Bleeders and fuses on every HV rail. +- **Clearances** (`hardware/kicad/plasma_dmd_psu.kicad_dru`): + - 3 mm between HV and LV, 1.3 mm between HV nets. + - Documented exceptions only inside or next to transistor and connector pins. +- **TO-220 tabs and heatsinks are live.** Each heatsink pin is on its collector net. +- **Track widths** come from IPC-2221 against the fuse currents (see `hardware/kicad/README.md`). + +## Workflow and tools + +- KiCad 10: `C:/Users/patri/AppData/Local/Programs/KiCad/10.0/bin/` (`kicad-cli.exe`, and `python.exe` with `pcbnew`). +- Freerouting 2.5.0 jar: `tools/freerouting/`, git-ignored. It needs **Java 25**: + `C:/Program Files/Eclipse Adoptium/jre-25.0.4.101-hotspot/bin/java.exe`. +- Pipeline (KiCad must be closed while the scripts run): + 1. `python hardware/kicad/gen_kicad.py` writes the schematic and the project net classes from `PARTS`. + It **keeps symbol UUIDs**, so the PCB stays linked. + 2. `python hardware/kicad/check_netlist.py` verifies every pin's net through kicad-cli. + 3. ` hardware/kicad/layout_pcb.py` adds, swaps and places footprints from `PLACE` and draws + the outline and silkscreen. **It deletes tracks and zones.** + 4. ` hardware/kicad/route_pcb.py [passes]` runs Freerouting: + - It routes with oversized tracks and vias, then shrinks them, which yields the clearances. + - It adds J2 escape stubs and heals T-junctions. + - It adds the bottom GND pour. + 5. `kicad-cli pcb drc --schematic-parity --refill-zones hardware/kicad/plasma_dmd_psu.kicad_pcb`. + The target is 0 errors. The 9 silkscreen warnings (TO-220 outline over the heatsink pins) are known. +- Once the user starts hand-editing the schematic or PCB in KiCad, stop regenerating with the scripts. + +## Gotchas learned the hard way + +- Bash heredocs passed through the tool can collapse `\\` and `\n` escapes. For Python with regexes + or escapes, use the Write/Edit tools, not `python - < **Paused (2026-10-24)** because of budget and safety concerns. See [docs/design-review.md](docs/design-review.md) +> for the latest review and cost estimate. + - [ ] Identify panel: manufacturer/part number from its label - [ ] Map the panel's power connector pins (WPC panel ≠ Stern CN2 pinout) and check if +12 V is used - [ ] Map the panel's 14-pin data connector diff --git a/docs/bom.md b/docs/bom.md index 18429d2..363418f 100644 --- a/docs/bom.md +++ b/docs/bom.md @@ -33,7 +33,7 @@ Prices are rough estimates. | 2 | 330 kΩ ½ W | R6, R11 | R6, R7 | | 1 | 2 kΩ 5 W | R13 | R8 | | 3 | 0.1 µF 500 V film | C6, C8, C9 | C3, C4, C7 | -| 3 | TO-220 heatsink | for Q3, Q5, Q6 | | +| 3 | Aavid 576802B03900G clip-on heatsink (~20 K/W), **live**: one per transistor, must not touch | HS1–HS3 on Q3, Q5, Q6 | | ## Additions diff --git a/docs/design-review.md b/docs/design-review.md new file mode 100644 index 0000000..267c5ad --- /dev/null +++ b/docs/design-review.md @@ -0,0 +1,191 @@ +# Design review and cost estimate + +*Review date 2026-10-24. Covers the proposed **module-only** PSU (rev 0.2), compared with the routed rev 0.1 +board, which used linear regulators copied from the Stern supply.* + +## Verdict + +The module-only design is **a better fit for this project** than rev 0.1: + +- No linear losses, no transistors, no heatsinks. +- About 20 fewer custom PCB parts. +- A board roughly half the size. +- It also makes the −100 V / −112 V relationship more robust (see §3). + +It is **not ready to build yet**. Four must-fix items (§8) block it: the unknown panel pinout, a weak point +in the watchdog drive, TVS clamp levels that depend on the panel's ratings, and buying genuine modules. + +Estimated cost: **about €90–190, typically about €120** (§9). + +--- + +## 1. Scope and assumptions + +- **Panel:** a 128×32 plasma DMD from a WPC game. Make, part number and pinouts are **still unknown**. +- **Rails needed** (PinWiki / Stern supply): about +62–65 V, −112 V, and −100 V. The −100 V rail is a + fixed 12 V offset from −112 V. Plus +5 V logic, and +12 V if the panel uses it. +- **Currents are unknown.** The design is sized against the fuse limits. Real currents get measured at bring-up. +- **Use:** a hobby device in a closed enclosure. It is not a certified product. + +## 2. Architecture (rev 0.2, module-only) + +``` +12 V brick (certified) ─F1 3A─┬─ TVS ─ Mini560 ──────────────── +5 V ─PTC─ TVS ─► ESP32, 74HCT245, panel logic + ├──────────────────────────────── +12 V ─JP1─► panel (if used) + └─ relay (watchdog) ─ +12V_HV ─┬─F2─ 45–390 V boost (65 V) ─F4─ RC ─ TVS ─► +65 V + └─F3─ iso 12→12 V ─ NCH6100HV (112 V, + to GND) + ─F5─ RC ─ TVS ─► −112 V + └─ B1212S stacked on −112 V ─ min-load ─► −100 V +``` + +## 3. Rail-by-rail review + +| Rail | Source | Regulation | Protection | Findings | +|---|---|---|---|---| +| +5 V | Mini560, fixed 5 V | Good (buck, fixed) | Add a PTC (about 1.5 A) and an SMBJ5.0A | Without the TVS, an HV-to-5V fault reaches the ESP32 and USB | +| +12 V | Brick, via F1 | Brick | F1 3 A, P6KE15A | OK | +| +65 V | 45–390 V boost board (8–32 V in, ≤0.2 A, 40 W) | Regulated, but uses **burst mode** at light load (jumpy ripple) | F4 100 mA, TVS clamp at about 72–78 V, RC filter, bleeder | Module is oversized but the most common one that reaches 65 V. **Bench-test the ripple and the no-load voltage** before connecting the panel. | +| −112 V | Isolated 12→12 V (about 6 W) + NCH6100HV at 112 V, floating (+ to GND) | NCH6100HV regulates | F5 100 mA, TVS clamp (P6KE130A class, check against the panel maximum), RC, bleeder | The 6 W isolated converter limits this rail to about **40–45 mA**. Check against the measured current. | +| −100 V | B1212S-1W stacked: − on −112 V, + gives −100 V | **Unregulated**, about ±10% → offset 10.8–13.2 V | 15 V zener across it, minimum-load resistor (about 10% load) | **Advantage:** the 12 V offset holds during start-up and shutdown too, because both rails move together. Rev 0.1 couldn't guarantee that. Consider a regulated 1–2 W isolated module if the offset tolerance matters. | + +Current direction checked: in the original circuit, Q6 *sourced* current into the −100 V node from GND, and the +panel returns it at −112 V. The B1212S sources current from its + output into −100 V, and it returns to its − +output at −112 V. Same direction, so the B1212S is never back-driven. + +## 4. Safety review + +Under IEC 62368-1 (AV/ICT equipment), anything above 120 V DC is class **ES3**, the highest-hazard class. +This design has −112 V, and up to about 180 V between +65 V and −112 V. + +| # | Topic | Status | +|---|---|---| +| 4.1 | Mains isolation | OK. Provided by the certified brick (Class II). | +| 4.2 | HV and LV **share one ground** (same as the original pinball supplies) | Only the 3 mm spacing (basic insulation, about 2.5 mm needed at 250 V, pollution degree 2) protects the 5 V side. **Needs:** the TVS on +5 V (a fault blows F4/F5), and no USB connected while HV is on, or a USB isolator. | +| 4.3 | Exposed HV | The HV modules (including the floating isolated converter output and the NCH6100HV at −112 V) and **the panel's own driver boards** are live. **Needs a tool-only enclosure with HV labels.** | +| 4.4 | Fault current | Each HV rail has a 100 mA fast fuse, and the modules limit current. A TVS clamp plus fuse turns a runaway module into a blown fuse, not a damaged panel. | +| 4.5 | Stored charge | Bleeders discharge the rails to below 60 V within about 2 s. | +| 4.6 | Fail-safe HV enable | The relay is normally open and driven by the watchdog. **But see 6.1: the drive is weak.** | +| 4.7 | Live heatsinks | **Gone** in rev 0.2 (no linear regulators). | +| 4.8 | Counterfeit modules | The NCH6100HV designer warns that the fakes are poor quality and **a fire hazard**. Buy from an authorized seller. | + +## 5. Thermal and efficiency + +| | rev 0.1 (linear) | rev 0.2 (modules) | +|---|---|---| +| Regulator losses at 20 mA per rail | about 0.5 W (Q3) + 0.4 W (Q5) + up to 2 W (Q6/R13) | 0 (only about 20 mW in the RC filters) | +| Worst case (fuse-limited) | about 10 W of heat, plus 3 heatsinks | Only module losses | +| Total heat, typical | about 4–6 W | about 1–3 W (boost modules at about 80–88% efficiency, isolated chain at about 70%) | +| Heatsinks / active cooling | 3 heatsinks, no fan | **None needed**. Ventilation slots are enough. | + +Power budget, typical: about 3–5 W for the panel HV, about 1–2 W for panel logic and the ESP32, plus losses. +That's about **8–12 W from the brick (≈ 1 A)**. The 36 W / 3 A brick has plenty of margin. + +## 6. Control and firmware + +1. **The watchdog gate drive is marginal (must fix).** + - The charge pump runs from the ESP32's 3.3 V output. After two diode drops it gives about 2.1–2.3 V at the 2N7000 gate. + - The 2N7000's turn-on threshold ranges from 0.8 to **3.0 V**. Some parts will never switch the relay module (about 5–10 mA). + - That fails safe (the HV stays off), but it isn't reliable. + - **Fix (no extra parts):** feed the charge pump from a spare 74HCT245 channel, which swings 5 V. That gives about 3.8 V at the gate. + - **Alternative:** replace the 2N7000 with a 2N3904/BC547 and a 10 kΩ base resistor. +2. The watchdog drop-out is about 1 s (C4 × R1). Using C4 = 1 µF gives about 0.1 s, which is less time with a stuck row on the panel. +3. **GPIO16/17** are free on ESP32-WROOM modules, but are used for PSRAM on WROVER modules. Check which module your Wemos board has. +4. The firmware scans in a busy loop for now. Wi-Fi interrupts will cause jitter and flicker. Later, move the scanning to a high-priority task, or to I2S/DMA output. +5. The panel signal polarities (enable, latch, row data) are still unverified. + +## 7. PCB and mechanics + +- **rev 0.1** (170 × 125 mm, routed, DRC clean) is obsolete if rev 0.2 is adopted. +- **rev 0.2 estimate:** about 100 × 80 mm. + - On the board: terminal blocks, 5 fuses, TVS clamps, RC filters, bleeders, the watchdog, the 74HCT245, the B1212S (SIP-4) and the panel connector. + - Off the board: the Mini560, the boost modules, the isolated converter and the relay module. +- Keep the 3 mm HV/LV spacing, the DRC rules and the routing scripts. They carry over. +- Mount the modules on standoffs inside the enclosure, keep the HV wires short, and give each module its own fuse. + +## 8. Findings + +| ID | Priority | Finding | Action | +|---|---|---|---| +| M1 | **Must** | The panel make, power and data pinouts are unknown. J2 follows the Stern CN2 order. | Photograph the label and connectors and map every pin. Wrong wiring can destroy the panel. | +| M2 | **Must** | The watchdog gate drive is marginal (6.1). | Drive the charge pump from the 74HCT245 (5 V), or use an NPN transistor. | +| M3 | **Must** | The TVS clamp levels depend on the panel's maximum voltages. | Choose them once the panel is identified. Clamp above the setpoint, below the panel maximum. | +| M4 | **Must** | Counterfeit NCH6100HV modules are a fire hazard. | Buy from an authorized seller. | +| S1 | Should | +5 V has no fuse or clamp. | Add a PTC of about 1.5 A and an SMBJ5.0A. | +| S2 | Should | Shared ground with USB. | No USB while HV is on, or use a USB isolator. | +| S3 | Should | Exposed HV on the modules and the panel. | Tool-only, vented enclosure with HV labels. | +| S4 | Should | The B1212S is unregulated. | Fit a minimum-load resistor and a 15 V zener, or use a regulated isolated module. | +| S5 | Should | Module quality varies (burst mode, no-load overshoot). | Bench-test each module on a dummy load before connecting the panel. | +| S6 | Should | The 6 W isolated converter limits −112 V to about 40–45 mA. | Measure the panel current. If it's higher, use a 10 W converter. | +| N1 | Nice | 1 s watchdog drop-out. | C4 = 1 µF for about 0.1 s. | +| N2 | Nice | GPIO16/17 on WROVER modules. | Check the module type. | +| N3 | Nice | Scan jitter with Wi-Fi. | Scan from a high-priority task or I2S/DMA. | +| N4 | Nice | RC filter values are a guess. | Tune after measuring with a scope. | +| N5 | Nice | Extra margin on the HV side. | Conformal coating. | + +## 9. Cost estimate (rev 0.2) + +Prices are rough, as of October 2026, in euros including VAT, for a single unit. AliExpress items vary. + +### Modules and power + +| Item | Qty | Estimate | +|---|---|---| +| 12 V 3 A brick, certified (Mean Well GST36E12 / GST36B12) | 1 | €17–25 | +| Mini560 5 V buck | 1 | €1–2 | +| 45–390 V adjustable boost module (+65 V) | 1 | €6–12 | +| NCH6100HV, **genuine** (−112 V) | 1 | €8–20 | +| Isolated DC-DC 12→12 V, 6 W, regulated (Mornsun YMD-6WR3 class) | 1 | €7–10 | +| B1212S-1W isolated (−100 V offset) | 1 | €1–3 (€4–6 for a regulated type) | +| Relay module, 5 V, opto | 1 | €1–2 | +| Wemos D1 mini ESP32 | 1 | €4–8 | +| **Subtotal** | | **€45–84** | + +### Board parts (Mouser / Farnell / TME / LCSC) + +| Item | Estimate | +|---|---| +| 5 × 5×20 mm fuse holder + fuses (3 A T, 2 × 1 A T, 2 × 100 mA F) + spares | €5–8 | +| TVS: P6KE15A, SMBJ5.0A, HV clamps × 2, 15 V zener | €2–3 | +| PTC 1.5 A | €0.5 | +| RC filters: 47 Ω 1 W + 22 µF/250 V, × 2–3 | €3–4 | +| Bleeders, minimum load, 2 LEDs | €1–2 | +| Watchdog parts (diodes, caps, transistor, resistors) | €1 | +| 74HCT245 + socket + decoupling | €1–2 | +| Terminal blocks × 7–8 (clone vs Phoenix) | €4–10 | +| Molex KK-396 8-pin header + housing + crimps | €2–4 | +| Header, jumper, standoffs, screws | €2 | +| **Subtotal** | **€22–37** | + +### Build + +| Item | Estimate | +|---|---| +| PCB, 5 pcs, 2-layer, about 100 × 80 mm (JLCPCB/PCBWay) + shipping | €10–25 | +| Vented plastic enclosure | €8–15 | +| Wire, ferrules, heat-shrink, 14-pin IDC ribbon for the panel data | €5–10 | +| Shipping / small-order fees (distributors, AliExpress) | €0–20 | +| **Subtotal** | **€23–70** | + +### Total + +| | Low | Typical | High | +|---|---|---|---| +| **rev 0.2, module-only** | **≈ €90** | **≈ €120** | **≈ €190** | +| rev 0.1, linear (for comparison) | +€15–25 for transistors, zeners, 3 heatsinks, 5 W resistor, plus about €5–15 for the larger PCB | | | +| Original route (replacement DMD PSU board) | €50–170 for the board, **plus** an AC transformer and mains wiring | | | + +## 10. Next steps + +1. Identify the panel (M1). That unblocks M3 and the J2 pinout. +2. Order the modules (genuine NCH6100HV, M4). Bench-test each one on a dummy load (S5). +3. Update the schematic, PCB, BOM and docs to rev 0.2, including M2, S1 and S4. +4. First power-up: series resistors and current measurements (S6). Then tune the RC filters (N4). + +## Sources + +- NCH6100HV price and counterfeit warning: [eBay listing](https://www.ebay.de/itm/296810265488), [neonixie-l (designer)](https://groups.google.com/g/neonixie-l/c/e8nm73UTEyk/m/e-skGAfqBAAJ), [Elecrow NCH8200HV](https://www.elecrow.com/nch8200hv-nixie-dc-dc-high-voltage-boost-power-converter.html) +- 45–390 V boost module: [AR5388 datasheet](https://uelectronics.com/wp-content/uploads/2026/07/AR5388-Convertidor-Boost-8-32V-a-45-390V-5A-Datasheet.pdf), [Sigmanortec](https://sigmanortec.ro/en/voltage-booster-module-zvs-dc-dc-45-390v-adjustable) +- B1212S-1W: [DigiKey B1212S-1WR3](https://digikey.cn/en/products/detail/mornsun-america-llc/B1212S-1WR3/13968708), [Robu](https://st.robu.in/product/b1212s-1wr3-dc-power-supply-module-1d1212-dc-dc-isolation-module-12v-to-12v1w-isolation-module) +- Mornsun 6 W isolated: [smbom URA2412YMD-6WR3](https://www.smbom.com/product/ura2412ymd-6wr3-3774098), [YMD-6WR3 datasheet](https://cdn.shopify.com/s/files/1/1180/9692/files/URA_YMD-6WR3.pdf) +- Mean Well GST36: [Farnell GST36E12](https://ie.farnell.com/mean-well/gst36e12-p1j/adaptor-ac-dc-12v-3a/dp/2815899), [RS GST36B12](https://de.rs-online.com/web/p/steckernetzteile/1176146) +- Rail voltages: [PinWiki Williams WPC](https://www.pinwiki.com/wiki/index.php?title=Williams_WPC) diff --git a/hardware/kicad/README.md b/hardware/kicad/README.md index b4b7384..5e31c60 100644 --- a/hardware/kicad/README.md +++ b/hardware/kicad/README.md @@ -29,6 +29,9 @@ Wire the isolated DC-DC output straight to NCH6100HV #2's input, off-board. Both | `check_netlist.py` | Exports the netlist with kicad-cli and checks every pin against `PARTS` | | `plasma_dmd_psu.kicad_sch` | Generated schematic (labels-per-pin style: connectivity is by net label) | | `plasma_dmd_psu.pdf` | Plot of the schematic | +| `plasma_dmd.pretty/`, `fp-lib-table` | Project footprint library (courtyard-less heatsink) | +| `layout_pcb.py`, `route_pcb.py` | Placement and autorouting scripts (see below) | +| `plasma_dmd_psu.kicad_dru` | Custom clearance rules | ```bash python hardware/kicad/gen_kicad.py @@ -43,7 +46,8 @@ stop using the generator once you start editing the schematic in KiCad. | Class | Nets | Clearance | Track | |---|---|---|---| | HV | +90V_RAW, +65V, −130V_RAW, −112V, −100V, HVP/HVN_MOD and all regulator internals | 1.3 mm (3.0 mm to LV via custom rules) | 0.6 mm | -| Power | GND, +12V*, +5V, +12V_PANEL | 0.3 mm | 1.0 mm | +| Power3A | +12V_IN, +12V (behind the 3 A fuse F1) | 0.3 mm | 1.5 mm | +| Power | GND (plus the bottom pour), +12V_HV/HVP/HVN, +5V, +12V_PANEL | 0.3 mm | 1.0 mm | | Default | Watchdog signals, LED cathode/anode nodes | 0.25 mm | 0.4 mm | ## PCB (rev 0.1) @@ -58,10 +62,49 @@ DRC is clean: 0 violations, 0 unconnected pads, schematic parity OK. A dashed silkscreen line marks the boundary, with DANGER text on both sides. - **J2 (panel)** straddles the boundary. Its LV pins (GND, +5V, +12V) leave towards the left, its HV pins towards the right. - **Terminal blocks** sit on the top and bottom edges, with wire entries facing outwards. -- **Heatsink space** is left above Q3, Q5 and Q6. +- **Heatsinks** HS1–HS3 (Aavid 576802B03900G clip-on, about 20 K/W) sit on Q3, Q5 and Q6. -> ⚠️ **The TO-220 tabs are live.** Q3's tab is at +90 V, Q5's at −130 V and Q6's at Q6_C. -> Give each transistor its own heatsink, keep the heatsinks apart, and don't let them touch anything. +> ⚠️ **The heatsinks are live.** Each one clips straight onto its transistor's tab: HS1 is at +90 V, +> HS2 at −130 V and HS3 at Q6_C. That's why each heatsink's solder pin is on the collector net, +> so the HV clearance rules also protect it. Never let the heatsinks touch each other or anything else. + +### Heatsinks + +- **Footprint:** `plasma_dmd:Heatsink_AAVID_576802B03900G_NoCourtyard` in the project library + `plasma_dmd.pretty`. It's a copy of KiCad's footprint with the courtyard and silkscreen outline + removed, because the clip wraps around the transistor and would always overlap its courtyard. + The outline is kept on F.Fab, and the footprint is marked "exempt from courtyard requirement". +- **Placement:** `layout_pcb.py` places each heatsink relative to its transistor (`heatsink_for()`), + with its tab face on the TO-220 tab. +- **Dissipation (estimate):** about 1–1.5 W per transistor. Bare TO-220 runs at about 62 K/W + (60–90 °C rise); with the heatsink, about 20 K/W (about 30 °C rise). +- **Project setting:** "PTH inside courtyard" is set to ignore, because each heatsink pin sits just + behind its tab, inside the transistor courtyard. Courtyard *overlaps* are still checked for all + other parts. +- **Remaining DRC items:** the 9 silkscreen warnings are the TO-220 outlines over the heatsink pins. + The fab clips silkscreen off pads, so they're harmless. + +### Current capacity + +Track widths follow IPC-2221 for 1 oz outer copper. Currents are estimated from the fuses. + +| Net | Max current (fuse) | Width | Capacity at 10 °C rise | +|---|---|---|---| +| +12V_IN, +12V | 3 A (F1) | 1.5 mm | ≈ 3.2 A | +| GND return | 3 A | 1.0 mm + solid bottom pour on the LV side | well above 3 A | +| +12V_HV | 2 A (F2 + F3) | 1.0 mm | ≈ 2.4 A | +| +12V_HVP, +12V_HVN | 1 A (F2, F3) | 1.0 mm | ≈ 2.4 A | +| +5V | about 1 A (unfused, from the Mini560) | 1.0 mm | ≈ 2.4 A | +| HV nets | 100 mA (F4, F5) | 0.6 mm | ≈ 1.7 A (width set by clearance, not current) | +| Signals | mA | 0.4 mm | ≈ 1.2 A | + +The 12 V input path, GND and +5V have no vias. + +- **Note on F3:** if the negative rail ever drew the full 100 mA that F5 allows (about 13 W), the + isolated converter plus the boost module would pull more than 1 A at 12 V. That would blow F3. + Measure the real HV current at bring-up. +- **Note on +5V:** the 5 V side isn't fused on its own. Consider a polyfuse (about 1.5 A) if the panel + or the ESP32 wiring could short. ### Clearance rules @@ -98,7 +141,7 @@ Once you start hand-editing the board in KiCad, stop running these scripts. They - [ ] Check every footprint against the parts you actually buy: fuse holders, the 12.5 mm caps, the R13 5 W size, and the terminal block pitch. - [ ] Map J2 to your panel's power connector. The current order follows the Stern CN2 connector. -- [ ] Check heatsink size and clearance for Q3/Q5/Q6. +- [ ] Check the heatsink orientation against the Aavid 5768 drawing. KiCad has no 3D model for it, so it isn't visible in the render. - [ ] Consider conformal coating on the HV side. - [ ] Get a second pair of eyes on the HV layout. diff --git a/hardware/kicad/fp-lib-table b/hardware/kicad/fp-lib-table new file mode 100644 index 0000000..4e3ab42 --- /dev/null +++ b/hardware/kicad/fp-lib-table @@ -0,0 +1,4 @@ +(fp_lib_table + (version 7) + (lib (name "plasma_dmd")(type "KiCad")(uri "${KIPRJMOD}/plasma_dmd.pretty")(options "")(descr "Project footprints")) +) diff --git a/hardware/kicad/gen_kicad.py b/hardware/kicad/gen_kicad.py index 0bb83b8..9df1556 100644 --- a/hardware/kicad/gen_kicad.py +++ b/hardware/kicad/gen_kicad.py @@ -35,6 +35,8 @@ FP_CP125 = "Capacitor_THT:CP_Radial_D12.5mm_P5.00mm" FP_HDR2 = "Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical" FP_KK8 = "Connector_Molex:Molex_KK-396_A-41791-0008_1x08_P3.96mm_Vertical" FP_HOLE = "MountingHole:MountingHole_3.2mm_M3" +# Clip-on TO-220 heatsink, ~20 K/W, solder pin. The tab is live, so the pin sits on the collector net. +FP_HS = "plasma_dmd:Heatsink_AAVID_576802B03900G_NoCourtyard" # project lib, see plasma_dmd.pretty def tb(n): @@ -79,6 +81,7 @@ PARTS = [ ("D5", "Device:D_Zener", "1N4760A 68V", FP_D41, {"K": "Q3_B", "A": "GND"}, 2), ("Q3", "Transistor_BJT:Q_NPN_BCE", "MJE15030", FP_TO220, {"C": "+90V_RAW", "B": "Q3_B", "E": "+65V"}, 2), ("C6", "Device:C", "0.1uF 500V", FP_CFILM, {"1": "+65V", "2": "GND"}, 2), + ("HS1", "Mechanical:Heatsink_Pad", "Aavid 576802B03900G (Q3, live +90V)", FP_HS, {"1": "+90V_RAW"}, 2), ("R6", "Device:R", "330k", FP_R, {"1": "+65V", "2": "GND"}, 2), # 4. Negative HV ("J6", "Connector:Screw_Terminal_01x02", "Isolated DC-DC in: VIN GND", tb(2), @@ -103,6 +106,8 @@ PARTS = [ ("Q6", "Transistor_BJT:Q_NPN_BCE", "MJE15030", FP_TO220, {"B": "Q6_B", "C": "Q6_C", "E": "-100V"}, 3), ("R13", "Device:R", "2k 5W", FP_R5W, {"1": "GND", "2": "Q6_C"}, 3), ("C9", "Device:C", "0.1uF 500V", FP_CFILM, {"1": "GND", "2": "-100V"}, 3), + ("HS2", "Mechanical:Heatsink_Pad", "Aavid 576802B03900G (Q5, live -130V)", FP_HS, {"1": "-130V_RAW"}, 3), + ("HS3", "Mechanical:Heatsink_Pad", "Aavid 576802B03900G (Q6, live Q6_C)", FP_HS, {"1": "Q6_C"}, 3), # 5. Panel connector (Stern 520-5138 CN2 order; verify against your panel!) ("J2", "Connector_Generic:Conn_01x08", "Panel power (Stern CN2 order)", FP_KK8, {"1": "-112V", "2": "-100V", "3": None, "4": "GND", "5": "GND", "6": "+5V", "7": "+12V_PANEL", "8": "+65V"}, 4), @@ -216,7 +221,10 @@ def snap(v): # N_LED1/N_LED2 sit a LED drop away from GND, so they stay in Default. HV_NETS = ["+90V_RAW", "+65V", "HVP_MOD", "Q2_E", "REF_P", "Q3_B", "-130V_RAW", "-112V", "-100V", "HVN_MOD", "Q4_E", "REF_N", "Q5_B", "REF_M", "Q6_B", "Q6_C"] -POWER_NETS = ["GND", "+12V", "+12V_IN", "+12V_HV", "+12V_HVP", "+12V_HVN", "+5V", "+12V_PANEL"] +# Track widths from IPC-2221 (1 oz outer copper): 1.5 mm carries ~3.2 A at 10 C rise, 1.0 mm ~2.4 A. +POWER3A_NETS = ["+12V", "+12V_IN"] # behind F1 (3 A) +# GND: 1.0 mm tracks plus the bottom-layer pour, which carries the 3 A return on the LV side +POWER_NETS = ["GND", "+12V_HV", "+12V_HVP", "+12V_HVN", "+5V", "+12V_PANEL"] # <= 2 A def netclass(name, clearance, track, priority): @@ -236,15 +244,21 @@ def write_project(): data["net_settings"] = { "classes": [ netclass("Default", 0.25, 0.4, 2147483647), - netclass("Power", 0.3, 1.0, 1), + netclass("Power3A", 0.3, 1.5, 1), + netclass("Power", 0.3, 1.0, 2), netclass("HV", 1.3, 0.6, 0) # HV <-> LV 3 mm comes from plasma_dmd_psu.kicad_dru, ], "meta": {"version": 5}, "net_colors": None, "netclass_assignments": None, "netclass_patterns": [{"netclass": "HV", "pattern": "/" + n} for n in HV_NETS] + + [{"netclass": "Power3A", "pattern": "/" + n} for n in POWER3A_NETS] + [{"netclass": "Power", "pattern": "/" + n} for n in POWER_NETS], } + # The heatsink pins sit just behind the TO-220 tab, inside the transistor courtyard. The heatsinks + # are the only courtyard-less parts, so this check adds nothing beyond courtyards_overlap. + sev = data.setdefault("board", {}).setdefault("design_settings", {}).setdefault("rule_severities", {}) + sev["pth_inside_courtyard"] = "ignore" pro.write_text(json.dumps(data, indent=2) + "\n", encoding="utf-8") diff --git a/hardware/kicad/layout_pcb.py b/hardware/kicad/layout_pcb.py index 07decc9..faad1e9 100644 --- a/hardware/kicad/layout_pcb.py +++ b/hardware/kicad/layout_pcb.py @@ -60,22 +60,23 @@ PLACE = { "Q5": (81.0, 70.0, 0), # heatsink space above (tab side) "Q6": (99.0, 70.0, 0), "R13": (114.0, 62.0, 0), # 5 W, runs warm: keep clear of caps - "D7": (74.0, 80.5, 0), - "D8": (90.0, 79.0, 0), - "R12": (106.0, 79.0, 0), - "C8": (122.0, 79.0, 0), - "D6": (68.0, 89.0, 0), - "R10": (82.0, 89.0, 0), - "R9": (105.0, 89.0, 0), - "Q4": (120.0, 90.0, 0), - "R11": (130.0, 89.0, 0), - "C9": (68.0, 99.0, 0), - "C7": (92.0, 101.0, 0), - "R7": (106.0, 99.0, 0), - "R8": (122.0, 99.0, 0), - "LED2": (144.0, 99.0, 0), - "F5": (120.0, 111.0, 0), + "D7": (74.0, 83.5, 0), + "D8": (90.0, 83.0, 0), + "R12": (106.0, 83.0, 0), + "C8": (122.0, 83.0, 0), + "D6": (68.0, 93.0, 0), + "R10": (82.0, 93.0, 0), + "R9": (105.0, 93.0, 0), + "Q4": (120.0, 94.0, 0), + "R11": (130.0, 93.0, 0), + "C9": (68.0, 103.0, 0), + "C7": (92.0, 105.0, 0), + "R7": (106.0, 103.0, 0), + "R8": (122.0, 103.0, 0), + "LED2": (144.0, 103.0, 0), + "F5": (120.0, 113.5, 0), "J7": (70.0, 118.5, 0), # NCH6100HV #2 output + # ---- heatsinks: see heatsink_for() ------------------------------------------------ # ---- mounting holes ------------------------------------------------------------ "H1": (4.0, 4.0, 0), "H2": (W - 4.0, 4.0, 0), @@ -83,13 +84,26 @@ PLACE = { "H4": (W - 4.0, H - 4.0, 0), } +HEATSINKS = {"HS1": "Q3", "HS2": "Q5", "HS3": "Q6"} + + +def heatsink_for(q): + """Aavid 576802B03900G on a TO-220-3_Vertical at rotation 0 (tab towards -y).""" + x, y, _ = PLACE[q] + return (x + 2.54, y - 3.6, 270) + + +for _hs, _q in HEATSINKS.items(): + PLACE[_hs] = heatsink_for(_q) + + SILK = [ # (text, x, y, size, layer) ("PLASMA DMD PSU rev 0.1", 24.0, 102.0, 1.5, "F.SilkS"), ("J1 12V IN", 13.5, 13.6, 1.0, "F.SilkS"), ("J3 MINI560", 31.6, 13.6, 1.0, "F.SilkS"), ("J8 ESP32", 52.1, 13.6, 1.0, "F.SilkS"), - ("J5 HV MOD 1", 71.1, 13.6, 1.0, "F.SilkS"), + ("J5 HV MOD 1", 68.0, 13.6, 1.0, "F.SilkS"), ("J4 RELAY MODULE", 21.2, 111.2, 1.0, "F.SilkS"), ("J6 ISO DC-DC IN", 41.5, 111.2, 1.0, "F.SilkS"), ("J7 HV MOD 2 OUT", 72.5, 111.2, 1.0, "F.SilkS"), @@ -109,6 +123,12 @@ def pt(x, y): return pcbnew.VECTOR2I(mm(OX + x), mm(OY + y)) +def lib_dir(lib): + """Project library (plasma_dmd.pretty next to the board) or a KiCad standard library.""" + local = HERE / f"{lib}.pretty" + return local if local.exists() else FP_DIR / f"{lib}.pretty" + + FP_DIR = Path(pcbnew.__file__).parents[3] / "share/kicad/footprints" # /10.0/share/... @@ -131,7 +151,7 @@ def sync_footprints(board): if not fpid or fpid == old.GetFPIDAsString(): continue lib, name = fpid.split(":") - new = pcbnew.FootprintLoad(str(FP_DIR / f"{lib}.pretty"), name) + new = pcbnew.FootprintLoad(str(lib_dir(lib)), name) new.SetFPID(pcbnew.LIB_ID(lib, name)) new.SetReference(ref) new.SetValue(old.GetValue()) @@ -148,8 +168,33 @@ def sync_footprints(board): print("swapped", ref, "->", fpid) +def add_missing_footprints(board): + """Add footprints for schematic symbols that are not on the board yet (like Update PCB, F8).""" + import gen_kicad + _, uuids = gen_kicad.existing_uuids() + present = {f.GetReference() for f in board.GetFootprints()} + for ref, lib_id, value, fpid, conns, _g in gen_kicad.PARTS: + if ref in present: + continue + lib, name = fpid.split(":") + fp = pcbnew.FootprintLoad(str(lib_dir(lib)), name) + fp.SetFPID(pcbnew.LIB_ID(lib, name)) + fp.SetReference(ref) + fp.SetValue(value) + fp.SetPath(pcbnew.KIID_PATH("/" + uuids[ref])) + fp.SetSheetname("/") + fp.SetSheetfile("plasma_dmd_psu.kicad_sch") + board.Add(fp) + for pad in fp.Pads(): + net = conns.get(pad.GetNumber()) + if net: + pad.SetNet(board.FindNet("/" + net)) + print("added", ref, "->", fpid) + + def main(): board = pcbnew.LoadBoard(str(BOARD)) + add_missing_footprints(board) sync_footprints(board) # clean previous layout output (outline, our silkscreen, tracks, vias, zones) @@ -175,9 +220,14 @@ def main(): f.Flip(f.GetPosition(), False) f.SetOrientationDegrees(rot) f.SetPosition(pt(x, y)) - f.SetLocked(ref.startswith(("J", "H"))) - if ref.startswith(("J", "H")): + fixed = ref.startswith("J") or (ref.startswith("H") and ref[1:].isdigit()) + f.SetLocked(fixed) + if fixed: f.Reference().SetVisible(False) # connectors are labelled by the SILK texts + if ref in HEATSINKS.values(): + f.Reference().SetPosition(pt(x + 2.54, y + 3.2)) # below the pins, clear of the heatsink pin + if ref in HEATSINKS: + f.Reference().SetPosition(pt(x + 9.5, y + 2.0)) # beside the heatsink # board outline with 2 mm corner radius r = 2.0 diff --git a/hardware/kicad/pcb-top.png b/hardware/kicad/pcb-top.png index dc73b91..6637f7d 100644 Binary files a/hardware/kicad/pcb-top.png and b/hardware/kicad/pcb-top.png differ diff --git a/hardware/kicad/plasma_dmd.pretty/Heatsink_AAVID_576802B03900G_NoCourtyard.kicad_mod b/hardware/kicad/plasma_dmd.pretty/Heatsink_AAVID_576802B03900G_NoCourtyard.kicad_mod new file mode 100644 index 0000000..cbbd66e --- /dev/null +++ b/hardware/kicad/plasma_dmd.pretty/Heatsink_AAVID_576802B03900G_NoCourtyard.kicad_mod @@ -0,0 +1,219 @@ +(footprint "Heatsink_AAVID_576802B03900G_NoCourtyard" + (version 20260206) + (generator "pcbnew") + (generator_version "10.0") + (layer "F.Cu") + (descr "Courtyard and silkscreen outline removed (outline kept on F.Fab): the clip wraps around its TO-220, so its courtyard would always overlap it. Heatsink, 14.48x12.7x19.05mm, TO-220/ TO-262, https://www.boydcorp.com/aavid-datasheets/Board-Level-Cooling-Plug-In-5768.pdf") + (tags "heatsink") + (property "Reference" "REF**" + (at 6.35 -8.5 0) + (layer "F.SilkS") + (uuid "07f046b7-ee46-436d-a8d8-54e735bd514a") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Value" "Heatsink_AAVID_576802B03900G" + (at 6.35 8.5 0) + (layer "F.Fab") + (uuid "0c915f93-8a39-4587-9dc9-356a06b61836") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 0) + (unlocked yes) + (layer "F.Fab") + (hide yes) + (uuid "715aca18-8f8d-4d48-a4e1-5c8463d0d1a0") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Description" "" + (at 0 0 0) + (unlocked yes) + (layer "F.Fab") + (hide yes) + (uuid "3dce55db-d6b0-43d7-b0f4-0d716ceb00b9") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (attr through_hole allow_missing_courtyard) + (duplicate_pad_numbers_are_jumpers no) + (fp_line + (start 0.405 -1.85) + (end 1.675 -1.85) + (stroke + (width 0.1) + (type solid) + ) + (layer "Dwgs.User") + (uuid "e2130da5-6bfd-4cff-a6e0-ce36fa9ed320") + ) + (fp_line + (start 0.405 1.85) + (end 1.675 1.85) + (stroke + (width 0.1) + (type solid) + ) + (layer "Dwgs.User") + (uuid "fad026d3-0846-44b8-ac9b-fc5c71aeb7d2") + ) + (fp_line + (start 0.45 -5) + (end 4.45 -5) + (stroke + (width 0.1) + (type solid) + ) + (layer "Dwgs.User") + (uuid "684b317f-96b2-4563-94b7-a9f9dbce19d3") + ) + (fp_line + (start 1.675 -5) + (end 1.675 5) + (stroke + (width 0.1) + (type solid) + ) + (layer "Dwgs.User") + (uuid "e1c3e282-b6b0-4028-8ab4-94f132389afb") + ) + (fp_line + (start 4.45 -5) + (end 4.45 5) + (stroke + (width 0.1) + (type solid) + ) + (layer "Dwgs.User") + (uuid "2be7b066-c2ff-480b-85f2-398b9dc58fb3") + ) + (fp_line + (start 4.45 5) + (end 0.45 5) + (stroke + (width 0.1) + (type solid) + ) + (layer "Dwgs.User") + (uuid "f5f503b5-f93a-4eb0-a9b7-af9692dd025f") + ) + (fp_line + (start -0.405 -6.35) + (end -0.405 6.35) + (stroke + (width 0.1) + (type solid) + ) + (layer "F.Fab") + (uuid "dd94d98b-8847-4ce0-b30f-d31c6f77bc25") + ) + (fp_line + (start -0.405 -6.35) + (end 12.295 -7.24) + (stroke + (width 0.1) + (type solid) + ) + (layer "F.Fab") + (uuid "b22575e4-0838-4d53-a202-9782ea057b6e") + ) + (fp_line + (start 0.405 -5.597) + (end 0.405 5.597) + (stroke + (width 0.1) + (type solid) + ) + (layer "F.Fab") + (uuid "a9099b8e-83d3-42a9-8fc6-6ccc4acfec5a") + ) + (fp_line + (start 0.405 -5.597) + (end 12.295 -6.43) + (stroke + (width 0.1) + (type solid) + ) + (layer "F.Fab") + (uuid "872fc3e3-6f14-4f00-aac2-46697acceeb4") + ) + (fp_line + (start 12.295 -7.24) + (end 12.295 7.24) + (stroke + (width 0.1) + (type solid) + ) + (layer "F.Fab") + (uuid "8f66f8ce-b782-479c-bb13-b0f17be7fa48") + ) + (fp_line + (start 12.295 7.24) + (end -0.405 6.35) + (stroke + (width 0.1) + (type solid) + ) + (layer "F.Fab") + (uuid "8bb6ea79-3367-4e22-b8d7-6f275fda6f15") + ) + (fp_line + (start 12.3 6.43) + (end 0.405 5.597) + (stroke + (width 0.1) + (type solid) + ) + (layer "F.Fab") + (uuid "ec19e519-279b-4d08-8288-be58fe8a8d44") + ) + (fp_text user "${REFERENCE}" + (at 6.35 0 0) + (layer "F.Fab") + (uuid "6ecf39c3-7bd4-4dc2-b3d8-015e1ce8efe0") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (pad "1" thru_hole oval + (at 0 0) + (size 2.6 3.78) + (drill oval 1.1 2.28) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (uuid "ec39e68d-6144-43b8-abb3-6034313acdbd") + ) + (embedded_fonts no) + (model "${KICAD10_3DMODEL_DIR}/Heatsink.3dshapes/Heatsink_AAVID_576802B03900G.step" + (offset + (xyz 0 0 0) + ) + (scale + (xyz 1 1 1) + ) + (rotate + (xyz 0 0 0) + ) + ) +) diff --git a/hardware/kicad/plasma_dmd_psu.kicad_pcb b/hardware/kicad/plasma_dmd_psu.kicad_pcb index 15cae9a..e6c199d 100644 --- a/hardware/kicad/plasma_dmd_psu.kicad_pcb +++ b/hardware/kicad/plasma_dmd_psu.kicad_pcb @@ -94,7 +94,7 @@ (descr "TO-220-3, Vertical, RM 2.54mm, see https://www.vishay.com/docs/66542/to-220-1.pdf") (tags "TO-220-3 Vertical RM 2.54mm") (property "Reference" "Q3" - (at 2.54 -4.1 0) + (at 2.54 3.2 0) (layer "F.SilkS") (uuid "3f91389e-840c-4fe3-a367-d864e78e5787") (effects @@ -1368,7 +1368,7 @@ (footprint "Diode_THT:D_DO-41_SOD81_P10.16mm_Horizontal" (layer "F.Cu") (uuid "14324c04-5428-42be-bbf0-7a19770608f4") - (at 190 129) + (at 190 133) (descr "Diode, DO-41_SOD81 series, Axial, Horizontal, pin pitch=10.16mm, length*diameter=5.2*2.7mm^2, https://www.diodes.com/assets/Package-Files/DO-41-Plastic.pdf") (tags "Diode DO-41_SOD81 series Axial Horizontal pin pitch 10.16mm length 5.2mm diameter 2.7mm") (property "Reference" "D8" @@ -1920,7 +1920,7 @@ (footprint "Diode_THT:D_DO-41_SOD81_P10.16mm_Horizontal" (layer "F.Cu") (uuid "1d9b2401-6fed-4017-986e-2d5e1bf34226") - (at 174 130.5) + (at 174 133.5) (descr "Diode, DO-41_SOD81 series, Axial, Horizontal, pin pitch=10.16mm, length*diameter=5.2*2.7mm^2, https://www.diodes.com/assets/Package-Files/DO-41-Plastic.pdf") (tags "Diode DO-41_SOD81 series Axial Horizontal pin pitch 10.16mm length 5.2mm diameter 2.7mm") (property "Reference" "D7" @@ -2200,7 +2200,7 @@ (descr "TO-220-3, Vertical, RM 2.54mm, see https://www.vishay.com/docs/66542/to-220-1.pdf") (tags "TO-220-3 Vertical RM 2.54mm") (property "Reference" "Q6" - (at 2.54 -4.1 0) + (at 2.54 3.2 0) (layer "F.SilkS") (uuid "26a0e9a2-0ab8-4c66-8db5-a21df31a2446") (effects @@ -2915,7 +2915,7 @@ (footprint "Capacitor_THT:C_Rect_L18.0mm_W5.0mm_P15.00mm_FKS3_FKP3" (layer "F.Cu") (uuid "247cd389-0fde-48f3-95b2-4a0a89520e0b") - (at 168 149) + (at 168 153) (descr "C, Rect series, Radial, pin pitch=15.00mm, length*width=18*5mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_3.pdf") (tags "C Rect series Radial pin pitch 15.00mm length 18mm width 5mm Capacitor") (property "Reference" "C9" @@ -3762,7 +3762,7 @@ (footprint "Resistor_THT:R_Axial_DIN0414_L11.9mm_D4.5mm_P15.24mm_Horizontal" (layer "F.Cu") (uuid "3a76b662-2532-4197-b545-6627ec1b02e2") - (at 222 149) + (at 222 153) (descr "Resistor, Axial_DIN0414 series, Axial, Horizontal, pin pitch=15.24mm, 2W, length*diameter=11.9*4.5mm^2, http://www.vishay.com/docs/20128/wkxwrx.pdf") (tags "Resistor Axial_DIN0414 series Axial Horizontal pin pitch 15.24mm 2W length 11.9mm diameter 4.5mm") (property "Reference" "R8" @@ -3953,7 +3953,7 @@ (footprint "Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal" (layer "F.Cu") (uuid "3c793587-6051-49ac-8d88-35f35caf7553") - (at 230 139) + (at 230 143) (descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf") (tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm") (property "Reference" "R11" @@ -6588,7 +6588,7 @@ (footprint "Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal" (layer "F.Cu") (uuid "6c8b1793-4892-4446-8800-9dc0053b7f54") - (at 206 149) + (at 206 153) (descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf") (tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm") (property "Reference" "R7" @@ -9430,7 +9430,7 @@ (footprint "Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal" (layer "F.Cu") (uuid "7980a1f0-9d07-4e14-a471-8fc6726a3ec6") - (at 205 139) + (at 205 143) (descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf") (tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm") (property "Reference" "R9" @@ -10840,6 +10840,228 @@ ) ) ) + (footprint "plasma_dmd:Heatsink_AAVID_576802B03900G_NoCourtyard" + (layer "F.Cu") + (uuid "9154a73b-91a5-485f-bc8b-b99889b9a22b") + (at 201.54 116.4 -90) + (descr "Courtyard and silkscreen outline removed (outline kept on F.Fab): the clip wraps around its TO-220, so its courtyard would always overlap it. Heatsink, 14.48x12.7x19.05mm, TO-220/ TO-262, https://www.boydcorp.com/aavid-datasheets/Board-Level-Cooling-Plug-In-5768.pdf") + (tags "heatsink") + (property "Reference" "HS3" + (at 2 -9.5 270) + (layer "F.SilkS") + (uuid "bae343c4-1e79-47f4-8c25-38239e813d15") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Value" "Aavid 576802B03900G (Q6, live Q6_C)" + (at 6.35 8.5 270) + (layer "F.Fab") + (uuid "56bb63f7-05e8-4687-bf67-63a64bcc502c") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 270) + (unlocked yes) + (layer "F.Fab") + (hide yes) + (uuid "33c63a38-c0ec-43c1-8030-db4e44c208b3") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Description" "" + (at 0 0 270) + (unlocked yes) + (layer "F.Fab") + (hide yes) + (uuid "ca4488a5-ed3e-4133-8f83-9d2326317d22") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (path "/8de79cdf-b68b-4232-a221-5163a3fde3c0") + (sheetname "/") + (sheetfile "plasma_dmd_psu.kicad_sch") + (attr through_hole allow_missing_courtyard) + (duplicate_pad_numbers_are_jumpers no) + (fp_line + (start 4.45 5) + (end 0.45 5) + (stroke + (width 0.1) + (type solid) + ) + (layer "Dwgs.User") + (uuid "40bd64c1-63fc-4bbc-83da-b9d5d2dc7f4a") + ) + (fp_line + (start 0.405 1.85) + (end 1.675 1.85) + (stroke + (width 0.1) + (type solid) + ) + (layer "Dwgs.User") + (uuid "842f56ba-1a2d-44b1-8046-f909b664be40") + ) + (fp_line + (start 0.405 -1.85) + (end 1.675 -1.85) + (stroke + (width 0.1) + (type solid) + ) + (layer "Dwgs.User") + (uuid "8a9d11ee-c01e-4d89-8efc-14e219046948") + ) + (fp_line + (start 0.45 -5) + (end 4.45 -5) + (stroke + (width 0.1) + (type solid) + ) + (layer "Dwgs.User") + (uuid "bca64044-59a6-4e5e-8844-fd4ebc24a087") + ) + (fp_line + (start 1.675 -5) + (end 1.675 5) + (stroke + (width 0.1) + (type solid) + ) + (layer "Dwgs.User") + (uuid "79c84904-b118-4ce8-83db-8a31f1e34128") + ) + (fp_line + (start 4.45 -5) + (end 4.45 5) + (stroke + (width 0.1) + (type solid) + ) + (layer "Dwgs.User") + (uuid "3e02224d-22d6-4f5b-a9a9-0c724f77ccc4") + ) + (fp_line + (start 12.295 7.24) + (end -0.405 6.35) + (stroke + (width 0.1) + (type solid) + ) + (layer "F.Fab") + (uuid "eab0fe84-6bde-458d-bbf6-072bb195f43a") + ) + (fp_line + (start 12.3 6.43) + (end 0.405 5.597) + (stroke + (width 0.1) + (type solid) + ) + (layer "F.Fab") + (uuid "22cd8746-efb7-41bd-8c5f-5c8a6ff19fa5") + ) + (fp_line + (start 0.405 -5.597) + (end 0.405 5.597) + (stroke + (width 0.1) + (type solid) + ) + (layer "F.Fab") + (uuid "74b70c2e-85b7-4a59-ade1-abbb81289a49") + ) + (fp_line + (start 0.405 -5.597) + (end 12.295 -6.43) + (stroke + (width 0.1) + (type solid) + ) + (layer "F.Fab") + (uuid "a5db651a-4309-4d6e-99f0-0accbe998c8c") + ) + (fp_line + (start -0.405 -6.35) + (end -0.405 6.35) + (stroke + (width 0.1) + (type solid) + ) + (layer "F.Fab") + (uuid "9184ad2a-f1e3-430e-b4ae-8b4bee37e23c") + ) + (fp_line + (start -0.405 -6.35) + (end 12.295 -7.24) + (stroke + (width 0.1) + (type solid) + ) + (layer "F.Fab") + (uuid "73d85247-fd8f-4d21-af5c-39281816764f") + ) + (fp_line + (start 12.295 -7.24) + (end 12.295 7.24) + (stroke + (width 0.1) + (type solid) + ) + (layer "F.Fab") + (uuid "dd001fa8-8588-49a7-9ed7-39dc6d440467") + ) + (fp_text user "${REFERENCE}" + (at 6.35 0 270) + (layer "F.Fab") + (uuid "699c9a34-b05c-4327-a775-8b2b37571629") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (pad "1" thru_hole oval + (at 0 0 270) + (size 2.6 3.78) + (drill oval 1.1 2.28) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (net "/Q6_C") + (uuid "fdbbf9ba-9186-4d4a-9f1d-73496099d96a") + ) + (embedded_fonts no) + (model "${KICAD10_3DMODEL_DIR}/Heatsink.3dshapes/Heatsink_AAVID_576802B03900G.step" + (offset + (xyz 0 0 0) + ) + (scale + (xyz 1 1 1) + ) + (rotate + (xyz 0 0 0) + ) + ) + ) (footprint "Package_TO_SOT_THT:TO-220-3_Vertical" (layer "F.Cu") (uuid "9725fc00-7b0f-4923-a864-6a87b8c18174") @@ -10847,7 +11069,7 @@ (descr "TO-220-3, Vertical, RM 2.54mm, see https://www.vishay.com/docs/66542/to-220-1.pdf") (tags "TO-220-3 Vertical RM 2.54mm") (property "Reference" "Q5" - (at 2.54 -4.1 0) + (at 2.54 3.2 0) (layer "F.SilkS") (uuid "3bb68bd7-ca4d-4a20-9c1f-b707520ee1b6") (effects @@ -11092,10 +11314,232 @@ ) ) ) + (footprint "plasma_dmd:Heatsink_AAVID_576802B03900G_NoCourtyard" + (layer "F.Cu") + (uuid "9b04ea64-cbc6-41b4-a091-da162eefc821") + (at 183.54 116.4 -90) + (descr "Courtyard and silkscreen outline removed (outline kept on F.Fab): the clip wraps around its TO-220, so its courtyard would always overlap it. Heatsink, 14.48x12.7x19.05mm, TO-220/ TO-262, https://www.boydcorp.com/aavid-datasheets/Board-Level-Cooling-Plug-In-5768.pdf") + (tags "heatsink") + (property "Reference" "HS2" + (at 2 -9.5 270) + (layer "F.SilkS") + (uuid "9f7f7fb8-fe58-477d-9609-2e9154a9a8ef") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Value" "Aavid 576802B03900G (Q5, live -130V)" + (at 6.35 8.5 270) + (layer "F.Fab") + (uuid "9be6a04a-24e1-4fc8-9bbe-bd35ef9b9fc2") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 270) + (unlocked yes) + (layer "F.Fab") + (hide yes) + (uuid "189aa43d-9e76-48dd-9973-eeaf1dc0a1b8") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Description" "" + (at 0 0 270) + (unlocked yes) + (layer "F.Fab") + (hide yes) + (uuid "69c48225-44ef-4be7-b884-a146cf2885c0") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (path "/e14552d1-e157-4a90-beed-d514ff8bc0f9") + (sheetname "/") + (sheetfile "plasma_dmd_psu.kicad_sch") + (attr through_hole allow_missing_courtyard) + (duplicate_pad_numbers_are_jumpers no) + (fp_line + (start 4.45 5) + (end 0.45 5) + (stroke + (width 0.1) + (type solid) + ) + (layer "Dwgs.User") + (uuid "0b654399-2f57-4f9b-9b09-29d6cfef9213") + ) + (fp_line + (start 0.405 1.85) + (end 1.675 1.85) + (stroke + (width 0.1) + (type solid) + ) + (layer "Dwgs.User") + (uuid "995672c8-04bd-4366-b15c-7fa736c300b5") + ) + (fp_line + (start 0.405 -1.85) + (end 1.675 -1.85) + (stroke + (width 0.1) + (type solid) + ) + (layer "Dwgs.User") + (uuid "c00fc631-bf59-4b83-bb3d-4eacf434939e") + ) + (fp_line + (start 0.45 -5) + (end 4.45 -5) + (stroke + (width 0.1) + (type solid) + ) + (layer "Dwgs.User") + (uuid "5b757f2e-fe95-4aba-a023-87640eb5e5d9") + ) + (fp_line + (start 1.675 -5) + (end 1.675 5) + (stroke + (width 0.1) + (type solid) + ) + (layer "Dwgs.User") + (uuid "5b798a81-c48e-49c4-933a-f90d32cad32a") + ) + (fp_line + (start 4.45 -5) + (end 4.45 5) + (stroke + (width 0.1) + (type solid) + ) + (layer "Dwgs.User") + (uuid "15f6e224-d393-4b27-9fd9-ccb05c6d5ab6") + ) + (fp_line + (start 12.295 7.24) + (end -0.405 6.35) + (stroke + (width 0.1) + (type solid) + ) + (layer "F.Fab") + (uuid "63795300-06e7-4d63-8e58-d1c288d795de") + ) + (fp_line + (start 12.3 6.43) + (end 0.405 5.597) + (stroke + (width 0.1) + (type solid) + ) + (layer "F.Fab") + (uuid "4cd9100e-eac1-47da-9a62-7d5e9f54be12") + ) + (fp_line + (start 0.405 -5.597) + (end 0.405 5.597) + (stroke + (width 0.1) + (type solid) + ) + (layer "F.Fab") + (uuid "62aa2249-3b1e-4f4c-a824-bf2447feed6a") + ) + (fp_line + (start 0.405 -5.597) + (end 12.295 -6.43) + (stroke + (width 0.1) + (type solid) + ) + (layer "F.Fab") + (uuid "6f47062b-18fc-4fdd-9331-717361801ffd") + ) + (fp_line + (start -0.405 -6.35) + (end -0.405 6.35) + (stroke + (width 0.1) + (type solid) + ) + (layer "F.Fab") + (uuid "b44279fb-3724-498e-852b-39b3c8ec62e2") + ) + (fp_line + (start -0.405 -6.35) + (end 12.295 -7.24) + (stroke + (width 0.1) + (type solid) + ) + (layer "F.Fab") + (uuid "c737fe84-257a-4167-be78-c9a52972ecf5") + ) + (fp_line + (start 12.295 -7.24) + (end 12.295 7.24) + (stroke + (width 0.1) + (type solid) + ) + (layer "F.Fab") + (uuid "101e01e8-270b-4ee4-8dc1-c5f5e6c36ba7") + ) + (fp_text user "${REFERENCE}" + (at 6.35 0 270) + (layer "F.Fab") + (uuid "a8ca5320-f841-4aa7-acdd-6e14164a3875") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (pad "1" thru_hole oval + (at 0 0 270) + (size 2.6 3.78) + (drill oval 1.1 2.28) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (net "/-130V_RAW") + (uuid "8a6a6d06-00d9-41db-a518-cdacf2b65cab") + ) + (embedded_fonts no) + (model "${KICAD10_3DMODEL_DIR}/Heatsink.3dshapes/Heatsink_AAVID_576802B03900G.step" + (offset + (xyz 0 0 0) + ) + (scale + (xyz 1 1 1) + ) + (rotate + (xyz 0 0 0) + ) + ) + ) (footprint "Resistor_THT:R_Axial_DIN0414_L11.9mm_D4.5mm_P15.24mm_Horizontal" (layer "F.Cu") (uuid "9ec2969e-bda4-458d-b16f-b5411152ba9b") - (at 182 139) + (at 182 143) (descr "Resistor, Axial_DIN0414 series, Axial, Horizontal, pin pitch=15.24mm, 2W, length*diameter=11.9*4.5mm^2, http://www.vishay.com/docs/20128/wkxwrx.pdf") (tags "Resistor Axial_DIN0414 series Axial Horizontal pin pitch 15.24mm 2W length 11.9mm diameter 4.5mm") (property "Reference" "R10" @@ -11657,7 +12101,7 @@ (footprint "Fuse:Fuseholder_Cylinder-5x20mm_Schurter_0031_8201_Horizontal_Open" (layer "F.Cu") (uuid "b07fc6a5-9053-447d-996b-a70e05b525d5") - (at 220 161) + (at 220 163.5) (descr "Fuseholder horizontal open, 5x20mm, 500V, 16A, Schurter 0031.8201, https://us.schurter.com/bundles/snceschurter/epim/_ProdPool_/newDS/en/typ_OGN.pdf") (tags "Fuseholder horizontal open 5x20 Schurter 0031.8201") (property "Reference" "F5" @@ -14128,7 +14572,7 @@ (footprint "Capacitor_THT:CP_Radial_D12.5mm_P5.00mm" (layer "F.Cu") (uuid "c48d51bc-e64e-4127-bd65-b1a89afa3639") - (at 192 151) + (at 192 155) (descr "CP, Radial series, Radial, pin pitch=5.00mm, diameter=12.5mm, height=20mm, Electrolytic Capacitor") (tags "CP Radial series Radial pin pitch 5.00mm diameter 12.5mm height 20mm Electrolytic Capacitor") (property "Reference" "C7" @@ -16876,7 +17320,7 @@ (footprint "LED_THT:LED_D5.0mm" (layer "F.Cu") (uuid "c9e4e58d-161e-411e-b9c9-2370d58afa57") - (at 244 149) + (at 244 153) (descr "LED, diameter 5.0mm, 2 pins, http://cdn-reichelt.de/documents/datenblatt/A500/LL-504BC2E-009.pdf, generated by kicad-footprint-generator") (tags "LED") (property "Reference" "LED2" @@ -17045,7 +17489,7 @@ ) ) (point - (at 245.27 149) + (at 245.27 153) (size 2) (layer "F.Fab") (uuid "3919014d-a793-43d5-a922-2aa811281c10") @@ -17279,7 +17723,7 @@ (footprint "Capacitor_THT:C_Rect_L18.0mm_W5.0mm_P15.00mm_FKS3_FKP3" (layer "F.Cu") (uuid "d8a8098a-0295-43ee-b073-9fea144879a4") - (at 222 129) + (at 222 133) (descr "C, Rect series, Radial, pin pitch=15.00mm, length*width=18*5mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_3.pdf") (tags "C Rect series Radial pin pitch 15.00mm length 18mm width 5mm Capacitor") (property "Reference" "C8" @@ -20602,7 +21046,7 @@ (footprint "Diode_THT:D_DO-35_SOD27_P7.62mm_Horizontal" (layer "F.Cu") (uuid "df3e88f2-86c4-49a9-80e5-3d90da006a19") - (at 168 139) + (at 168 143) (descr "Diode, DO-35_SOD27 series, Axial, Horizontal, pin pitch=7.62mm, length*diameter=4*2mm^2, http://www.diodes.com/_files/packages/DO-35.pdf") (tags "Diode DO-35_SOD27 series Axial Horizontal pin pitch 7.62mm length 4mm diameter 2mm") (property "Reference" "D6" @@ -21243,6 +21687,228 @@ ) ) ) + (footprint "plasma_dmd:Heatsink_AAVID_576802B03900G_NoCourtyard" + (layer "F.Cu") + (uuid "e39162f3-87e8-499a-a9a8-8848f07d15d0") + (at 183.54 98.4 -90) + (descr "Courtyard and silkscreen outline removed (outline kept on F.Fab): the clip wraps around its TO-220, so its courtyard would always overlap it. Heatsink, 14.48x12.7x19.05mm, TO-220/ TO-262, https://www.boydcorp.com/aavid-datasheets/Board-Level-Cooling-Plug-In-5768.pdf") + (tags "heatsink") + (property "Reference" "HS1" + (at 2 -9.5 270) + (layer "F.SilkS") + (uuid "bdf58a4a-40f6-4919-a8e3-59ad16a06eab") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Value" "Aavid 576802B03900G (Q3, live +90V)" + (at 6.35 8.5 270) + (layer "F.Fab") + (uuid "2b737b67-5d32-43dc-9c26-c20976f3c202") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 270) + (unlocked yes) + (layer "F.Fab") + (hide yes) + (uuid "19f20035-6247-42c4-b062-9ab7a4954913") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Description" "" + (at 0 0 270) + (unlocked yes) + (layer "F.Fab") + (hide yes) + (uuid "07e43221-f7e5-4d6d-b2b3-5630b0438c80") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (path "/50efcea2-afe9-4c84-86c2-2c74ffde9503") + (sheetname "/") + (sheetfile "plasma_dmd_psu.kicad_sch") + (attr through_hole allow_missing_courtyard) + (duplicate_pad_numbers_are_jumpers no) + (fp_line + (start 4.45 5) + (end 0.45 5) + (stroke + (width 0.1) + (type solid) + ) + (layer "Dwgs.User") + (uuid "e3302a72-9fce-4960-b6d9-0ee007a3d952") + ) + (fp_line + (start 0.405 1.85) + (end 1.675 1.85) + (stroke + (width 0.1) + (type solid) + ) + (layer "Dwgs.User") + (uuid "6aed4104-32e5-4069-9d88-cf04f201a310") + ) + (fp_line + (start 0.405 -1.85) + (end 1.675 -1.85) + (stroke + (width 0.1) + (type solid) + ) + (layer "Dwgs.User") + (uuid "86c77193-41ef-44c6-9604-586025f140b7") + ) + (fp_line + (start 0.45 -5) + (end 4.45 -5) + (stroke + (width 0.1) + (type solid) + ) + (layer "Dwgs.User") + (uuid "496a3373-dc12-4eb9-bf2f-10d1225f0c51") + ) + (fp_line + (start 1.675 -5) + (end 1.675 5) + (stroke + (width 0.1) + (type solid) + ) + (layer "Dwgs.User") + (uuid "b1daec8d-ac75-4aec-be93-4f4c342b3ea3") + ) + (fp_line + (start 4.45 -5) + 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@@ -22608,7 +23274,7 @@ (footprint "Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal" (layer "F.Cu") (uuid "e71bc1b8-f397-4789-9f62-82e37bad085a") - (at 206 129) + (at 206 133) (descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf") (tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm") (property "Reference" "R12" @@ -22799,7 +23465,7 @@ (footprint "Package_TO_SOT_THT:TO-92_Inline_Wide" (layer "F.Cu") (uuid "f3387944-8690-4e30-ab62-94ba22d977a2") - (at 220 140) + (at 220 144) (descr "TO-92 leads in-line, wide, drill 0.75mm (see NXP sot054_po.pdf)") (tags "to-92 sc-43 sc-43a sot54 PA33 transistor") (property "Reference" "Q4" @@ -23040,7 +23706,7 @@ (type default) ) (layer "F.SilkS") - (uuid "91ce2953-887f-4aa8-80a2-ac2c285d25fb") + (uuid "a96c1869-5734-48bd-8170-b1e6f03dc12c") ) (gr_line (start 161 68.5) @@ -23050,7 +23716,7 @@ (type default) ) (layer "F.SilkS") - (uuid "d71dcdb4-c6ab-4890-955e-8a476405c336") + (uuid "f2910a50-d717-4edb-a48d-6897fbc7108e") ) (gr_line (start 161 72) @@ -23060,7 +23726,7 @@ (type default) ) (layer "F.SilkS") - (uuid "f34dfa7d-2386-44b5-b76c-418522302c6d") + (uuid "0ca4fac7-c2eb-4af8-99fd-67f37402612b") ) (gr_line (start 161 75.5) @@ -23070,7 +23736,7 @@ (type default) ) (layer "F.SilkS") - (uuid "4e0947cc-4279-4997-925d-8acc2867958d") + (uuid "ae232e9a-779f-47e6-ac22-19f3cd6236ef") ) (gr_line (start 161 79) @@ -23080,7 +23746,7 @@ (type default) ) (layer "F.SilkS") - (uuid "955b9cff-8d0b-4290-900f-e82d356a1461") + (uuid "ec616a32-7950-465a-9bdf-249abd54d897") ) (gr_line (start 161 82.5) @@ -23090,7 +23756,7 @@ (type default) ) (layer "F.SilkS") - (uuid "cf06bd37-a0f1-456e-8e3d-229e891f97ae") + (uuid "18dc0f26-bda4-49fb-bcd8-fd4565806b89") ) (gr_line (start 161 86) @@ -23100,7 +23766,7 @@ (type default) ) (layer "F.SilkS") - (uuid "3a007021-8ac4-40e5-9a39-48fe1a1974e7") + (uuid "f3c9bace-a6b8-4185-af13-740d282ce52b") ) (gr_line (start 161 89.5) @@ -23110,7 +23776,7 @@ (type default) ) (layer "F.SilkS") - (uuid "140ccb43-4abf-4cce-a9b6-48bb7357d16b") + (uuid "075668f0-8949-408e-8f7d-e13470f40c11") ) (gr_line (start 161 135) @@ -23120,7 +23786,7 @@ (type default) ) (layer "F.SilkS") - (uuid "d85fc393-1702-40bf-bf92-7fd6db21c259") + (uuid "df5ec07b-9fb9-4591-8675-0795efb10acd") ) (gr_line (start 161 138.5) @@ -23130,7 +23796,7 @@ (type default) ) (layer "F.SilkS") - (uuid "66d8219b-80b3-47f4-a58b-76a0ca7b4b41") + (uuid "c04f9f4b-143a-4ff9-976e-30358acd19fb") ) (gr_line (start 161 142) @@ -23140,7 +23806,7 @@ (type default) ) (layer "F.SilkS") - (uuid "56537059-d2fb-45c4-aa43-2417d9ca3ebb") + (uuid "f298fda4-610f-4f70-ae48-d92d1cb531c7") ) (gr_line (start 161 145.5) @@ -23150,7 +23816,7 @@ (type default) ) (layer "F.SilkS") - (uuid "399e6756-e4ca-4ba1-a843-5358a82c38df") + (uuid "ed4b0db2-c6fa-495e-b1f7-de4c111a70a8") ) (gr_line (start 161 149) @@ -23160,7 +23826,7 @@ (type default) ) (layer "F.SilkS") - (uuid "0e4223ed-93c9-4fb3-927b-a3e54992124a") + (uuid "2be3d734-5e5c-4cf0-b5ce-8439f4d73e6c") ) (gr_line (start 161 152.5) @@ -23170,7 +23836,7 @@ (type default) ) (layer "F.SilkS") - (uuid "b5b9584c-21fe-4489-b431-e023640bd799") + (uuid "362fae0c-c65c-4969-8bd3-a3978f412863") ) (gr_line (start 161 156) @@ -23180,7 +23846,7 @@ (type default) ) (layer "F.SilkS") - (uuid "e0313250-3951-4d20-ae39-f49196c2b9b2") + (uuid "d4653511-78a7-4a11-8d56-90e2f0470bbc") ) (gr_line (start 161 159.5) @@ -23190,7 +23856,7 @@ (type default) ) (layer "F.SilkS") - (uuid "abae973c-429b-4e16-99f1-019b59e8a61a") + (uuid "1388342d-4bfd-492a-a55a-2095974c6c3f") ) (gr_line (start 161 163) @@ -23200,7 +23866,7 @@ (type default) ) (layer "F.SilkS") - (uuid "4b6d4106-b52d-47fa-815f-616acdd6df9a") + (uuid "8b5494ce-bad1-4e7b-aa22-d665afa7701e") ) (gr_line (start 161 166.5) @@ -23210,7 +23876,7 @@ (type default) ) (layer "F.SilkS") - (uuid "c4e94ff2-fb7c-4f25-aaad-c428ab515be7") + (uuid "71e8afec-ff68-4889-a536-635b8ed5d827") ) (gr_line (start 161 170) @@ -23220,7 +23886,7 @@ (type default) ) (layer "F.SilkS") - (uuid "7982b41c-832e-442d-98d1-17dfc1576549") + (uuid "2a4dc843-5981-4659-bac7-48a072754169") ) (gr_arc (start 100 52) @@ -23231,7 +23897,7 @@ (type default) ) (layer "Edge.Cuts") - (uuid "6e4be85a-358b-4d85-8b75-177159f0d820") + (uuid "5599a376-43f5-4d15-870f-0f5295e6f16c") ) (gr_line (start 100 173) @@ -23241,7 +23907,7 @@ (type default) ) (layer "Edge.Cuts") - (uuid "69f886c2-f6ed-44b1-8b54-693acb042be5") + (uuid "ff58ce72-f663-4adc-a362-21d4bcd0d8a5") ) (gr_line (start 102 50) @@ -23251,7 +23917,7 @@ (type default) ) (layer "Edge.Cuts") - (uuid "15c2b7c2-5abb-4061-a8d1-dfeb49f8f97f") + (uuid "106caed9-574d-45af-a52f-1feeac93de46") ) (gr_arc (start 102 175) @@ -23262,7 +23928,7 @@ (type default) ) (layer "Edge.Cuts") - (uuid "8285443e-b70d-40ac-8f94-06b733e1d8ac") + (uuid "afccf2bf-05ee-4972-b249-02c635f29c32") ) (gr_arc (start 268 50) @@ -23273,7 +23939,7 @@ (type default) ) (layer "Edge.Cuts") - (uuid "52ea6f3a-0db4-4d10-9ab7-ed726602e1d5") + (uuid "56638a14-3098-40ef-a488-b7615c94b2cf") ) (gr_line (start 268 175) @@ -23283,7 +23949,7 @@ (type default) ) (layer "Edge.Cuts") - (uuid "3b7ae5ac-340b-43f0-a52a-b5fddde54897") + (uuid "38dbe03e-5fb3-47db-9421-19982078ea60") ) (gr_line (start 270 52) @@ -23293,7 +23959,7 @@ (type default) ) (layer "Edge.Cuts") - (uuid "8541361e-c61b-4ec1-a408-a8e5292b864f") + (uuid "14882e27-b03c-463a-9717-a8ab2dc45a93") ) (gr_arc (start 270 173) @@ -23304,23 +23970,12 @@ (type default) ) (layer "Edge.Cuts") - (uuid "f517c1c5-dbd2-490a-9d4c-d2b053133ed1") - ) - (gr_text "J5 HV MOD 1" - (at 171.1 63.6 0) - (layer "F.SilkS") - (uuid "8b1dcbde-7153-4c0f-9db7-2ef0f1720613") - (effects - (font - (size 1 1) - (thickness 0.135) - ) - ) + (uuid "af312f3e-6abd-4810-bd3c-1f155ffd2fc2") ) (gr_text "J1 12V IN" (at 113.5 63.6 0) (layer "F.SilkS") - (uuid "062d3a07-0bf9-4dc3-a214-f96886ecda8f") + (uuid "172dc6e9-9e96-4b64-bf8c-ff6a001ba7b7") (effects (font (size 1 1) @@ -23331,7 +23986,7 @@ (gr_text "J4 RELAY MODULE" (at 121.2 161.2 0) (layer "F.SilkS") - (uuid "44828193-1af2-433b-96ad-46c43d244a67") + (uuid "3b4108e8-fe23-4f48-af33-002165ee63f2") (effects (font (size 1 1) @@ -23342,7 +23997,7 @@ (gr_text "J3 MINI560" (at 131.6 63.6 0) (layer "F.SilkS") - (uuid "d875f9c2-4c54-49de-bad7-f0558d38442f") + (uuid "671da75d-1e17-442c-8a3f-7873dfa6b425") (effects (font (size 1 1) @@ -23353,7 +24008,7 @@ (gr_text "J6 ISO DC-DC IN" (at 141.5 161.2 0) (layer "F.SilkS") - (uuid "81a7cd58-625f-4da7-85d6-5ba5dfbfbc4d") + (uuid "8adecdc6-0abc-47e8-91f4-2f8afcf83204") (effects (font (size 1 1) @@ -23364,7 +24019,7 @@ (gr_text "J8 ESP32" (at 152.1 63.6 0) (layer "F.SilkS") - (uuid "57229b3d-677d-44b2-9843-151ae1595fa2") + (uuid "4df66da5-37c2-4ceb-a842-1efc1dede982") (effects (font (size 1 1) @@ -23375,7 +24030,18 @@ (gr_text "J2 PANEL" (at 161 94 0) (layer "F.SilkS") - (uuid "cbfb58c9-321b-4a72-9345-d440e994c5eb") + (uuid "08b2d2b5-7978-4598-9980-83b468ca6785") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (gr_text "J5 HV MOD 1" + (at 168 63.6 0) + (layer "F.SilkS") + (uuid "b1a13408-b580-47ff-a697-bb392f21e335") (effects (font (size 1 1) @@ -23386,7 +24052,7 @@ (gr_text "J7 HV MOD 2 OUT" (at 172.5 161.2 0) (layer "F.SilkS") - (uuid "3c4bd980-d441-4543-98d9-a69599df6c49") + (uuid "232b7b2c-5449-46ce-ba2a-54a23da8aa9c") (effects (font (size 1 1) @@ -23397,7 +24063,7 @@ (gr_text "up to 220V" (at 258 95.5 0) (layer "F.SilkS") - (uuid "bef9d1f1-4756-4c1f-8415-462afb21709a") + (uuid "6113ebf5-abdd-47b7-b661-8df4832381c2") (effects (font (size 1.2 1.2) @@ -23408,7 +24074,7 @@ (gr_text "PLASMA DMD PSU rev 0.1" (at 124 152 0) (layer "F.SilkS") - (uuid "80d1574b-bf29-4e48-b4ad-717e3a987541") + (uuid "12db9ed5-2f81-4581-9eb1-6b47e03d59e9") (effects (font (size 1.5 1.5) @@ -23419,7 +24085,7 @@ (gr_text "HIGH VOLTAGE" (at 258 92 0) (layer "F.SilkS") - (uuid "84e6ff26-8f57-4b89-9785-30f901a4a4e8") + (uuid "ae77c7d7-665a-42d5-a527-dc479f125cb1") (effects (font (size 1.6 1.6) @@ -23430,7 +24096,7 @@ (gr_text "DANGER" (at 258 88 0) (layer "F.SilkS") - (uuid "6537c834-0e72-41c2-bb7d-d1f31994ac97") + (uuid "e2235df1-088b-4252-b94d-44f0181a4be4") (effects (font (size 2 2) @@ -23441,7 +24107,7 @@ (gr_text "DANGER HIGH VOLTAGE" (at 252 120 0) (layer "B.SilkS") - (uuid "31a54b6a-001c-43b0-8b80-9db3fe3b5e74") + (uuid "c80be351-d990-4084-9c21-06f941b77162") (effects (font (size 1.6 1.6) @@ -23450,45 +24116,13 @@ (justify mirror) ) ) - (segment - (start 226 83) - (end 227 82) - (width 0.6) - (layer "F.Cu") - (net "/Q3_B") - (uuid "6829dc27-b640-4d3f-83bd-561750777f33") - ) - (segment - (start 216.3842 91.6827) - (end 222.2917 85.7752) - (width 0.6) - (layer "F.Cu") - (net "/Q3_B") - (uuid "99f0732c-70ba-4a3a-97cb-981f3cd7224d") - ) - (segment - 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50.514493) + (xy 101.966158 50.50292) (xy 101.991137 50.501134) (xy 102.0089 50.5005) (xy 102.065892 50.5005) + (xy 267.934108 50.5005) (xy 267.9911 50.5005) ) ) ) diff --git a/hardware/kicad/plasma_dmd_psu.kicad_pro b/hardware/kicad/plasma_dmd_psu.kicad_pro index 295ec33..309b120 100644 --- a/hardware/kicad/plasma_dmd_psu.kicad_pro +++ b/hardware/kicad/plasma_dmd_psu.kicad_pro @@ -112,7 +112,7 @@ "nonmirrored_text_on_back_layer": "warning", "npth_inside_courtyard": "error", "padstack": "warning", - "pth_inside_courtyard": "error", + "pth_inside_courtyard": "ignore", "shorting_items": "error", "silk_edge_clearance": "warning", "silk_over_copper": "warning", @@ -542,13 +542,32 @@ "microvia_drill": 0.1, "name": "Power", "pcb_color": "rgba(0, 0, 0, 0.000)", - "priority": 1, + "priority": 2, "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 1.0, "tuning_profile": "", "via_diameter": 1.0, "via_drill": 0.5, "wire_width": 6 + }, + { + "bus_width": 12, + "clearance": 0.3, + "diff_pair_gap": 0.25, + "diff_pair_via_gap": 0.25, + "diff_pair_width": 0.2, + "line_style": 0, + "microvia_diameter": 0.3, + "microvia_drill": 0.1, + "name": "Power3A", + "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": 1, + "schematic_color": "rgba(0, 0, 0, 0.000)", + "track_width": 1.5, + "tuning_profile": "", + "via_diameter": 1.0, + "via_drill": 0.5, + "wire_width": 6 } ], "meta": { @@ -622,17 +641,17 @@ "pattern": "/Q6_C" }, { - "netclass": "Power", - "pattern": "/GND" - }, - { - "netclass": "Power", + "netclass": "Power3A", "pattern": "/+12V" }, { - "netclass": "Power", + "netclass": "Power3A", "pattern": "/+12V_IN" }, + { + "netclass": "Power", + "pattern": "/GND" + }, { "netclass": "Power", "pattern": "/+12V_HV" diff --git a/hardware/kicad/plasma_dmd_psu.kicad_sch b/hardware/kicad/plasma_dmd_psu.kicad_sch index 5e33298..6c33b49 100644 --- a/hardware/kicad/plasma_dmd_psu.kicad_sch +++ b/hardware/kicad/plasma_dmd_psu.kicad_sch @@ -3262,6 +3262,141 @@ ) (embedded_fonts no) ) + (symbol "Mechanical:Heatsink_Pad" + (pin_names + (offset 0) + ) + (exclude_from_sim no) + (in_bom yes) + (on_board yes) + (in_pos_files yes) + (duplicate_pin_numbers_are_jumpers no) + (property "Reference" "HS" + (at 0 5.715 0) + (show_name no) + (do_not_autoplace no) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Value" "Heatsink_Pad" + (at 0 3.81 0) + (show_name no) + (do_not_autoplace no) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Footprint" "" + (at 0.3048 -1.27 0) + (show_name no) + (do_not_autoplace no) + (hide yes) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Datasheet" "" + (at 0.3048 -1.27 0) + (show_name no) + (do_not_autoplace no) + (hide yes) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Description" "Heatsink with electrical connection, 1 pin" + (at 0 0 0) + (show_name no) + (do_not_autoplace no) + (hide yes) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "ki_keywords" "thermal heat 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1) (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid "faf13b3c-2135-4a95-9f8d-cc48288e173b") - (property "Reference" "H3" (at 246.38 369.57 0) (effects (font (size 1.27 1.27)) (justify left))) - (property "Value" "M3" (at 246.38 372.11 0) (effects (font (size 1.27 1.27)) (justify left))) - (property "Footprint" "MountingHole:MountingHole_3.2mm_M3" (at 241.3 370.84 0) (effects (font (size 1.27 1.27)) (hide yes))) - (property "Datasheet" "" (at 241.3 370.84 0) (effects (font (size 1.27 1.27)) (hide yes))) + (property "Reference" "H3" (at 246.38 425.45 0) (effects (font (size 1.27 1.27)) (justify left))) + (property "Value" "M3" (at 246.38 427.99 0) (effects (font (size 1.27 1.27)) (justify left))) + (property "Footprint" "MountingHole:MountingHole_3.2mm_M3" (at 241.3 426.72 0) (effects (font (size 1.27 1.27)) (hide yes))) + (property "Datasheet" "" (at 241.3 426.72 0) (effects (font (size 1.27 1.27)) (hide yes))) (instances (project "plasma_dmd_psu" (path "/d8fec46f-dde9-4522-8610-66699deb1f29" (reference "H3") (unit 1)))) ) - (symbol (lib_id "Mechanical:MountingHole") (at 292.1 370.84 0) (unit 1) + (symbol (lib_id "Mechanical:MountingHole") (at 292.1 426.72 0) (unit 1) (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid "16e16879-49c4-4a5e-8c7e-e75d11458984") - (property "Reference" "H4" (at 297.18 369.57 0) (effects (font (size 1.27 1.27)) (justify left))) - (property "Value" "M3" (at 297.18 372.11 0) (effects (font (size 1.27 1.27)) (justify left))) - (property "Footprint" "MountingHole:MountingHole_3.2mm_M3" (at 292.1 370.84 0) (effects (font (size 1.27 1.27)) (hide yes))) - (property "Datasheet" "" (at 292.1 370.84 0) (effects (font (size 1.27 1.27)) (hide yes))) + (property "Reference" "H4" (at 297.18 425.45 0) (effects (font (size 1.27 1.27)) (justify left))) + (property "Value" "M3" (at 297.18 427.99 0) (effects (font (size 1.27 1.27)) (justify left))) + (property "Footprint" "MountingHole:MountingHole_3.2mm_M3" (at 292.1 426.72 0) (effects (font (size 1.27 1.27)) (hide yes))) + (property "Datasheet" "" (at 292.1 426.72 0) (effects (font (size 1.27 1.27)) (hide yes))) (instances (project "plasma_dmd_psu" (path "/d8fec46f-dde9-4522-8610-66699deb1f29" (reference "H4") (unit 1)))) ) - (text "1. 12 V input and +5 V (Mini560 off-board)" (exclude_from_sim no) (at 25.4 33.02 0) (effects (font (size 2.54 2.54) (bold yes)) (justify left bottom)) (uuid "696f9e14-8950-4bfd-b3e5-c947d0f982ef")) - (text "2. HV enable relay + hardware watchdog (relay module off-board)" (exclude_from_sim no) (at 25.4 86.36000000000001 0) (effects (font (size 2.54 2.54) (bold yes)) (justify left bottom)) (uuid "1cfaece6-d6b8-4eb7-806a-de537e0accbf")) - (text "3. Positive HV: NCH6100HV #1 off-board + original regulator -> +65 V" (exclude_from_sim no) (at 25.4 167.64000000000001 0) (effects (font (size 2.54 2.54) (bold yes)) (justify left bottom)) (uuid "e6a6861f-5483-4196-a906-f0239d886493")) - (text "4. Negative HV: isolated DC-DC + NCH6100HV #2 off-board (FLOATING at -130 V) + regulator -> -112 / -100 V" (exclude_from_sim no) (at 25.4 248.92000000000002 0) (effects (font (size 2.54 2.54) (bold yes)) (justify left bottom)) (uuid "0f20b32e-cf4a-44ed-93fc-23456462caa1")) - (text "5. Panel connector and mounting" (exclude_from_sim no) (at 25.4 358.14000000000004 0) (effects (font (size 2.54 2.54) (bold yes)) (justify left bottom)) (uuid "3e6a265e-fa13-4c77-a6a8-ab8dabe9ecc4")) - (text "Plasma DMD - 12 V DC PSU carrier board (rev 0.1, unverified)\nConnectivity is by net labels: every pin has a stub + label. Off-board modules connect via J3-J7.\nPanel voltages are set by zeners D5 (68 V -> about +65 V) and D7+D8 (113 V -> about -112 / -100 V), copied from Stern 520-5138-00.\nSAFETY: keep >= 3 mm clearance (more is better) between HV nets (+90V_RAW, +65V, -130V_RAW, -112V, -100V, HVN_MOD, HVP_MOD) and low-voltage nets.\nJ2 pin order follows the Stern CN2 connector: map it to YOUR panel before use. Pin 3 is the key position." (exclude_from_sim no) (at 25.4 12.7 0) (effects (font (size 1.778 1.778)) (justify left top)) (uuid "2e69a240-2cb4-4ff7-b393-745da68f3c08")) + (text "1. 12 V input and +5 V (Mini560 off-board)" (exclude_from_sim no) (at 25.4 33.02 0) (effects (font (size 2.54 2.54) (bold yes)) (justify left bottom)) (uuid "b6a9c868-daf6-456f-9ac1-eb4e3e8f4e4e")) + (text "2. HV enable relay + hardware watchdog (relay module off-board)" (exclude_from_sim no) (at 25.4 86.36000000000001 0) (effects (font (size 2.54 2.54) (bold yes)) (justify left bottom)) (uuid "cb9dc0c6-36cf-4709-a809-085b37bf0ef2")) + (text "3. Positive HV: NCH6100HV #1 off-board + original regulator -> +65 V" (exclude_from_sim no) (at 25.4 167.64000000000001 0) (effects (font (size 2.54 2.54) (bold yes)) (justify left bottom)) (uuid "70c5affa-110e-400b-8f82-449882a0af34")) + (text "4. Negative HV: isolated DC-DC + NCH6100HV #2 off-board (FLOATING at -130 V) + regulator -> -112 / -100 V" (exclude_from_sim no) (at 25.4 276.86 0) (effects (font (size 2.54 2.54) (bold yes)) (justify left bottom)) (uuid "14cf960f-e444-49fa-8025-66ce2769d020")) + (text "5. Panel connector and mounting" (exclude_from_sim no) (at 25.4 414.02 0) (effects (font (size 2.54 2.54) (bold yes)) (justify left bottom)) (uuid "b0ad5729-8e94-48ce-a5d5-3d8ef4b13887")) + (text "Plasma DMD - 12 V DC PSU carrier board (rev 0.1, unverified)\nConnectivity is by net labels: every pin has a stub + label. Off-board modules connect via J3-J7.\nPanel voltages are set by zeners D5 (68 V -> about +65 V) and D7+D8 (113 V -> about -112 / -100 V), copied from Stern 520-5138-00.\nSAFETY: keep >= 3 mm clearance (more is better) between HV nets (+90V_RAW, +65V, -130V_RAW, -112V, -100V, HVN_MOD, HVP_MOD) and low-voltage nets.\nJ2 pin order follows the Stern CN2 connector: map it to YOUR panel before use. Pin 3 is the key position." (exclude_from_sim no) (at 25.4 12.7 0) (effects (font (size 1.778 1.778)) (justify left top)) (uuid "9b14549c-93f3-4e4b-af49-d958ee0276ff")) (sheet_instances (path "/" (page "1"))) ) diff --git a/hardware/kicad/plasma_dmd_psu.pdf b/hardware/kicad/plasma_dmd_psu.pdf index ba205ff..4ff4662 100644 Binary files a/hardware/kicad/plasma_dmd_psu.pdf and b/hardware/kicad/plasma_dmd_psu.pdf differ diff --git a/hardware/kicad/route_pcb.py b/hardware/kicad/route_pcb.py index 5c88906..a791f57 100644 --- a/hardware/kicad/route_pcb.py +++ b/hardware/kicad/route_pcb.py @@ -26,7 +26,8 @@ PASSES = int(sys.argv[1]) if len(sys.argv) > 1 else 100 # (routing clearance + half the width difference) from its neighbours. This gets 3 mm HV <-> LV # and 1.3 mm HV <-> HV while tracks can still squeeze out between transistor pins. # class: (routing width um, routing clearance um, final width mm) -ROUTE = {"kicad_default": (1800, 250, 0.4), "Power": (2400, 300, 1.0), "HV": (2100, 650, 0.6)} +ROUTE = {"kicad_default": (1800, 250, 0.4), "Power": (2400, 300, 1.0), "Power3A": (2900, 300, 1.5), + "HV": (2100, 650, 0.6)} VIA_ROUTE_UM, VIA_FINAL_MM, VIA_DRILL_MM = 2300, 1.0, 0.5 # same trick for vias HV_TO_LV_UM = 2450 # + (2.1 - 0.6) / 2 after shrinking = 3.2 mm @@ -62,7 +63,7 @@ def add_connector_stubs(board, ref="J2", length=5.0): """ fp = board.FindFootprintByReference(ref) # final widths: a router track must end on the stub copper itself, which still holds after shrinking - widths = {"HV": ROUTE["HV"][2], "Power": ROUTE["Power"][2]} + widths = {k: v[2] for k, v in ROUTE.items()} for pad in fp.Pads(): net = pad.GetNet() name = net.GetNetname() if net else "" @@ -81,6 +82,55 @@ def add_connector_stubs(board, ref="J2", length=5.0): board.Add(t) +def _closest_on_segment(p, a, b): + ax, ay, bx, by = a.x, a.y, b.x, b.y + dx, dy = bx - ax, by - ay + L2 = dx * dx + dy * dy + u = 0.0 if L2 == 0 else max(0.0, min(1.0, ((p.x - ax) * dx + (p.y - ay) * dy) / L2)) + cx, cy = ax + u * dx, ay + u * dy + return int(round(cx)), int(round(cy)), ((p.x - cx) ** 2 + (p.y - cy) ** 2) ** 0.5 + + +def heal_t_junctions(board, reach_mm=1.6): + """After shrinking, a track that joined another track mid-way (a T-junction) can end beside + the narrowed copper. Snap such dangling ends onto the centre line of the same-net track.""" + traces = [t for t in board.GetTracks() if t.Type() == pcbnew.PCB_TRACE_T] + vias = [t for t in board.GetTracks() if t.Type() == pcbnew.PCB_VIA_T] + pads = [p for f in board.GetFootprints() for p in f.Pads()] + reach = pcbnew.FromMM(reach_mm) + fixed = 0 + for t in traces: + for is_start in (True, False): + p = t.GetStart() if is_start else t.GetEnd() + net, layer = t.GetNetCode(), t.GetLayer() + if any(pd.GetNetCode() == net and pd.IsOnLayer(layer) and pd.HitTest(p) for pd in pads): + continue + if any(v.GetNetCode() == net and v.GetPosition() == p for v in vias): + continue + best, touching = None, False + for o in traces: + if o is t or o.GetNetCode() != net or o.GetLayer() != layer: + continue + if p in (o.GetStart(), o.GetEnd()): + touching = True + break + cx, cy, d = _closest_on_segment(p, o.GetStart(), o.GetEnd()) + if d <= o.GetWidth() / 2: + touching = True + break + if d <= reach and (best is None or d < best[2]): + best = (cx, cy, d) + if touching or best is None: + continue + q = pcbnew.VECTOR2I(best[0], best[1]) + if is_start: + t.SetStart(q) + else: + t.SetEnd(q) + fixed += 1 + return fixed + + def unconnected(board): board.BuildConnectivity() return board.GetConnectivity().GetUnconnectedCount(False) @@ -199,6 +249,7 @@ def main(): if not pcbnew.ImportSpecctraSES(board, str(ses)): raise SystemExit("SES import failed") shrink_tracks(board) + print("healed T-junctions:", heal_t_junctions(board)) remove_dangling_stubs(board) add_gnd_plane(board) pcbnew.ZONE_FILLER(board).Fill(board.Zones())