Heatsinks, wider 12 V tracks, design review; pause project
- PCB rev 0.1: Power3A class (1.5 mm) for the 12 V input path, Aavid clip-on heatsinks on Q3/Q5/Q6 (project footprint library), T-junction healing and via shrink in the router; DRC 0 errors - Current-capacity and heatsink documentation - CLAUDE.md with project decisions, workflow and gotchas - docs/design-review.md: review of a module-only PSU (rev 0.2) and cost estimate - Project paused for budget and safety reasons Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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mangavalkandClaude Opus 5.5 committed
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@@ -60,22 +60,23 @@ PLACE = {
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"Q5": (81.0, 70.0, 0), # heatsink space above (tab side)
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"Q6": (99.0, 70.0, 0),
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"R13": (114.0, 62.0, 0), # 5 W, runs warm: keep clear of caps
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"D7": (74.0, 80.5, 0),
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"D8": (90.0, 79.0, 0),
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"R12": (106.0, 79.0, 0),
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"C8": (122.0, 79.0, 0),
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"D6": (68.0, 89.0, 0),
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"R10": (82.0, 89.0, 0),
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"R9": (105.0, 89.0, 0),
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"Q4": (120.0, 90.0, 0),
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"R11": (130.0, 89.0, 0),
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"C9": (68.0, 99.0, 0),
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"C7": (92.0, 101.0, 0),
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"R7": (106.0, 99.0, 0),
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"R8": (122.0, 99.0, 0),
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"LED2": (144.0, 99.0, 0),
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"F5": (120.0, 111.0, 0),
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"D7": (74.0, 83.5, 0),
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"D8": (90.0, 83.0, 0),
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"R12": (106.0, 83.0, 0),
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"C8": (122.0, 83.0, 0),
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"D6": (68.0, 93.0, 0),
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"R10": (82.0, 93.0, 0),
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"R9": (105.0, 93.0, 0),
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"Q4": (120.0, 94.0, 0),
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"R11": (130.0, 93.0, 0),
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"C9": (68.0, 103.0, 0),
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"C7": (92.0, 105.0, 0),
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"R7": (106.0, 103.0, 0),
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"R8": (122.0, 103.0, 0),
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"LED2": (144.0, 103.0, 0),
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"F5": (120.0, 113.5, 0),
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"J7": (70.0, 118.5, 0), # NCH6100HV #2 output
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# ---- heatsinks: see heatsink_for() ------------------------------------------------
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# ---- mounting holes ------------------------------------------------------------
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"H1": (4.0, 4.0, 0),
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"H2": (W - 4.0, 4.0, 0),
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@@ -83,13 +84,26 @@ PLACE = {
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"H4": (W - 4.0, H - 4.0, 0),
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}
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HEATSINKS = {"HS1": "Q3", "HS2": "Q5", "HS3": "Q6"}
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def heatsink_for(q):
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"""Aavid 576802B03900G on a TO-220-3_Vertical at rotation 0 (tab towards -y)."""
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x, y, _ = PLACE[q]
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return (x + 2.54, y - 3.6, 270)
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for _hs, _q in HEATSINKS.items():
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PLACE[_hs] = heatsink_for(_q)
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SILK = [
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# (text, x, y, size, layer)
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("PLASMA DMD PSU rev 0.1", 24.0, 102.0, 1.5, "F.SilkS"),
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("J1 12V IN", 13.5, 13.6, 1.0, "F.SilkS"),
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("J3 MINI560", 31.6, 13.6, 1.0, "F.SilkS"),
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("J8 ESP32", 52.1, 13.6, 1.0, "F.SilkS"),
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("J5 HV MOD 1", 71.1, 13.6, 1.0, "F.SilkS"),
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("J5 HV MOD 1", 68.0, 13.6, 1.0, "F.SilkS"),
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("J4 RELAY MODULE", 21.2, 111.2, 1.0, "F.SilkS"),
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("J6 ISO DC-DC IN", 41.5, 111.2, 1.0, "F.SilkS"),
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("J7 HV MOD 2 OUT", 72.5, 111.2, 1.0, "F.SilkS"),
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@@ -109,6 +123,12 @@ def pt(x, y):
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return pcbnew.VECTOR2I(mm(OX + x), mm(OY + y))
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def lib_dir(lib):
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"""Project library (plasma_dmd.pretty next to the board) or a KiCad standard library."""
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local = HERE / f"{lib}.pretty"
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return local if local.exists() else FP_DIR / f"{lib}.pretty"
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FP_DIR = Path(pcbnew.__file__).parents[3] / "share/kicad/footprints" # <KiCad>/10.0/share/...
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@@ -131,7 +151,7 @@ def sync_footprints(board):
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if not fpid or fpid == old.GetFPIDAsString():
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continue
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lib, name = fpid.split(":")
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new = pcbnew.FootprintLoad(str(FP_DIR / f"{lib}.pretty"), name)
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new = pcbnew.FootprintLoad(str(lib_dir(lib)), name)
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new.SetFPID(pcbnew.LIB_ID(lib, name))
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new.SetReference(ref)
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new.SetValue(old.GetValue())
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@@ -148,8 +168,33 @@ def sync_footprints(board):
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print("swapped", ref, "->", fpid)
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def add_missing_footprints(board):
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"""Add footprints for schematic symbols that are not on the board yet (like Update PCB, F8)."""
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import gen_kicad
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_, uuids = gen_kicad.existing_uuids()
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present = {f.GetReference() for f in board.GetFootprints()}
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for ref, lib_id, value, fpid, conns, _g in gen_kicad.PARTS:
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if ref in present:
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continue
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lib, name = fpid.split(":")
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fp = pcbnew.FootprintLoad(str(lib_dir(lib)), name)
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fp.SetFPID(pcbnew.LIB_ID(lib, name))
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fp.SetReference(ref)
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fp.SetValue(value)
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fp.SetPath(pcbnew.KIID_PATH("/" + uuids[ref]))
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fp.SetSheetname("/")
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fp.SetSheetfile("plasma_dmd_psu.kicad_sch")
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board.Add(fp)
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for pad in fp.Pads():
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net = conns.get(pad.GetNumber())
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if net:
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pad.SetNet(board.FindNet("/" + net))
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print("added", ref, "->", fpid)
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def main():
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board = pcbnew.LoadBoard(str(BOARD))
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add_missing_footprints(board)
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sync_footprints(board)
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# clean previous layout output (outline, our silkscreen, tracks, vias, zones)
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@@ -175,9 +220,14 @@ def main():
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f.Flip(f.GetPosition(), False)
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f.SetOrientationDegrees(rot)
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f.SetPosition(pt(x, y))
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f.SetLocked(ref.startswith(("J", "H")))
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if ref.startswith(("J", "H")):
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fixed = ref.startswith("J") or (ref.startswith("H") and ref[1:].isdigit())
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f.SetLocked(fixed)
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if fixed:
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f.Reference().SetVisible(False) # connectors are labelled by the SILK texts
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if ref in HEATSINKS.values():
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f.Reference().SetPosition(pt(x + 2.54, y + 3.2)) # below the pins, clear of the heatsink pin
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if ref in HEATSINKS:
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f.Reference().SetPosition(pt(x + 9.5, y + 2.0)) # beside the heatsink
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# board outline with 2 mm corner radius
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r = 2.0
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