Heatsinks, wider 12 V tracks, design review; pause project

- PCB rev 0.1: Power3A class (1.5 mm) for the 12 V input path, Aavid
  clip-on heatsinks on Q3/Q5/Q6 (project footprint library), T-junction
  healing and via shrink in the router; DRC 0 errors
- Current-capacity and heatsink documentation
- CLAUDE.md with project decisions, workflow and gotchas
- docs/design-review.md: review of a module-only PSU (rev 0.2) and cost
  estimate
- Project paused for budget and safety reasons

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

hardware/kicad/README.md

@@ -29,6 +29,9 @@ Wire the isolated DC-DC output straight to NCH6100HV #2's input, off-board. Both
 | `check_netlist.py` | Exports the netlist with kicad-cli and checks every pin against `PARTS` |
 | `plasma_dmd_psu.kicad_sch` | Generated schematic (labels-per-pin style: connectivity is by net label) |
 | `plasma_dmd_psu.pdf` | Plot of the schematic |
+| `plasma_dmd.pretty/`, `fp-lib-table` | Project footprint library (courtyard-less heatsink) |
+| `layout_pcb.py`, `route_pcb.py` | Placement and autorouting scripts (see below) |
+| `plasma_dmd_psu.kicad_dru` | Custom clearance rules |
 
 ```bash
 python hardware/kicad/gen_kicad.py
@@ -43,7 +46,8 @@ stop using the generator once you start editing the schematic in KiCad.
 | Class | Nets | Clearance | Track |
 |---|---|---|---|
 | HV | +90V_RAW, +65V, −130V_RAW, −112V, −100V, HVP/HVN_MOD and all regulator internals | 1.3 mm (3.0 mm to LV via custom rules) | 0.6 mm |
-| Power | GND, +12V*, +5V, +12V_PANEL | 0.3 mm | 1.0 mm |
+| Power3A | +12V_IN, +12V (behind the 3 A fuse F1) | 0.3 mm | 1.5 mm |
+| Power | GND (plus the bottom pour), +12V_HV/HVP/HVN, +5V, +12V_PANEL | 0.3 mm | 1.0 mm |
 | Default | Watchdog signals, LED cathode/anode nodes | 0.25 mm | 0.4 mm |
 
 ## PCB (rev 0.1)
@@ -58,10 +62,49 @@ DRC is clean: 0 violations, 0 unconnected pads, schematic parity OK.
   A dashed silkscreen line marks the boundary, with DANGER text on both sides.
 - **J2 (panel)** straddles the boundary. Its LV pins (GND, +5V, +12V) leave towards the left, its HV pins towards the right.
 - **Terminal blocks** sit on the top and bottom edges, with wire entries facing outwards.
-- **Heatsink space** is left above Q3, Q5 and Q6.
+- **Heatsinks** HS1–HS3 (Aavid 576802B03900G clip-on, about 20 K/W) sit on Q3, Q5 and Q6.
 
-> ⚠️ **The TO-220 tabs are live.** Q3's tab is at +90 V, Q5's at −130 V and Q6's at Q6_C.
-> Give each transistor its own heatsink, keep the heatsinks apart, and don't let them touch anything.
+> ⚠️ **The heatsinks are live.** Each one clips straight onto its transistor's tab: HS1 is at +90 V,
+> HS2 at −130 V and HS3 at Q6_C. That's why each heatsink's solder pin is on the collector net,
+> so the HV clearance rules also protect it. Never let the heatsinks touch each other or anything else.
+
+### Heatsinks
+
+- **Footprint:** `plasma_dmd:Heatsink_AAVID_576802B03900G_NoCourtyard` in the project library
+  `plasma_dmd.pretty`. It's a copy of KiCad's footprint with the courtyard and silkscreen outline
+  removed, because the clip wraps around the transistor and would always overlap its courtyard.
+  The outline is kept on F.Fab, and the footprint is marked "exempt from courtyard requirement".
+- **Placement:** `layout_pcb.py` places each heatsink relative to its transistor (`heatsink_for()`),
+  with its tab face on the TO-220 tab.
+- **Dissipation (estimate):** about 1–1.5 W per transistor. Bare TO-220 runs at about 62 K/W
+  (60–90 °C rise); with the heatsink, about 20 K/W (about 30 °C rise).
+- **Project setting:** "PTH inside courtyard" is set to ignore, because each heatsink pin sits just
+  behind its tab, inside the transistor courtyard. Courtyard *overlaps* are still checked for all
+  other parts.
+- **Remaining DRC items:** the 9 silkscreen warnings are the TO-220 outlines over the heatsink pins.
+  The fab clips silkscreen off pads, so they're harmless.
+
+### Current capacity
+
+Track widths follow IPC-2221 for 1 oz outer copper. Currents are estimated from the fuses.
+
+| Net | Max current (fuse) | Width | Capacity at 10 °C rise |
+|---|---|---|---|
+| +12V_IN, +12V | 3 A (F1) | 1.5 mm | ≈ 3.2 A |
+| GND return | 3 A | 1.0 mm + solid bottom pour on the LV side | well above 3 A |
+| +12V_HV | 2 A (F2 + F3) | 1.0 mm | ≈ 2.4 A |
+| +12V_HVP, +12V_HVN | 1 A (F2, F3) | 1.0 mm | ≈ 2.4 A |
+| +5V | about 1 A (unfused, from the Mini560) | 1.0 mm | ≈ 2.4 A |
+| HV nets | 100 mA (F4, F5) | 0.6 mm | ≈ 1.7 A (width set by clearance, not current) |
+| Signals | mA | 0.4 mm | ≈ 1.2 A |
+
+The 12 V input path, GND and +5V have no vias.
+
+- **Note on F3:** if the negative rail ever drew the full 100 mA that F5 allows (about 13 W), the
+  isolated converter plus the boost module would pull more than 1 A at 12 V. That would blow F3.
+  Measure the real HV current at bring-up.
+- **Note on +5V:** the 5 V side isn't fused on its own. Consider a polyfuse (about 1.5 A) if the panel
+  or the ESP32 wiring could short.
 
 ### Clearance rules
 
@@ -98,7 +141,7 @@ Once you start hand-editing the board in KiCad, stop running these scripts. They
 
 - [ ] Check every footprint against the parts you actually buy: fuse holders, the 12.5 mm caps, the R13 5 W size, and the terminal block pitch.
 - [ ] Map J2 to your panel's power connector. The current order follows the Stern CN2 connector.
-- [ ] Check heatsink size and clearance for Q3/Q5/Q6.
+- [ ] Check the heatsink orientation against the Aavid 5768 drawing. KiCad has no 3D model for it, so it isn't visible in the render.
 - [ ] Consider conformal coating on the HV side.
 - [ ] Get a second pair of eyes on the HV layout.