Add routed PSU carrier board layout (rev 0.1)
- Placement script (layout_pcb.py): LV left, HV right, panel connector on the boundary, terminal blocks on the edges, heatsink space for the TO-220s - Freerouting-based routing script (route_pcb.py) that routes with oversized tracks/vias and shrinks them, giving 3 mm HV-to-LV and 1.3 mm HV-to-HV - Custom DRC rules (plasma_dmd_psu.kicad_dru) with documented exceptions - Wide TO-92 footprints; schematic generator now keeps symbol UUIDs - DRC: 0 violations, 0 unconnected pads, schematic parity OK Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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mangavalkandClaude Opus 5.5 committed
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"""Place footprints, draw the outline and silkscreen for the PSU carrier board.
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Run with KiCad's bundled Python (KiCad must not have the board open):
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"C:/Users/patri/AppData/Local/Programs/KiCad/10.0/bin/python.exe" hardware/kicad/layout_pcb.py
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Coordinates below are board-local mm (origin = top-left corner of the board, y down).
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Positions are the footprint origin (pad 1). Axial parts run left to right, pad 1 on the left.
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"""
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from pathlib import Path
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import pcbnew
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HERE = Path(__file__).parent
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BOARD = HERE / "plasma_dmd_psu.kicad_pcb"
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OX, OY = 100.0, 50.0 # board origin on the page
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W, H = 170.0, 125.0 # board size
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HV_X = 61.0 # LV | HV boundary (silkscreen)
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# ref: (x, y, rotation_deg)
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PLACE = {
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# Phoenix MKDS terminals: wire entry is on the footprint's +y side, so top-edge blocks are
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# rotated 180 (entry up) and bottom-edge blocks stay at 0 (entry down).
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# ---- low-voltage side (left) -------------------------------------------------
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"J1": (16.08, 6.5, 180), # 12 V in
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"J3": (39.24, 6.5, 180), # Mini560
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"J8": (57.16, 6.5, 180), # ESP32
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"F1": (8.0, 22.0, 0),
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"D1": (8.0, 31.0, 0),
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"C1": (28.0, 35.0, 0),
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"C2": (40.0, 22.0, 0),
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"C3": (37.0, 34.0, 0),
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"D3": (37.0, 41.0, 0),
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"D2": (37.0, 47.0, 0),
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"C4": (50.0, 41.0, 0),
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"R1": (37.0, 53.0, 0),
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"Q1": (44.0, 60.0, 0),
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"JP1": (50.0, 72.0, 0),
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"F2": (8.0, 76.0, 0),
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"F3": (8.0, 90.0, 0),
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"J4": (11.0, 118.5, 0), # relay module
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"J6": (40.0, 118.5, 0), # isolated DC-DC input
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# ---- positive HV (top right) -------------------------------------------------
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"J5": (76.16, 6.5, 180), # NCH6100HV #1
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"F4": (66.0, 20.0, 0),
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"C5": (96.0, 20.0, 0),
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"R2": (110.0, 20.0, 0),
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"R3": (127.0, 20.0, 0),
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"LED1": (148.0, 20.0, 0),
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"D4": (68.0, 32.0, 0),
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"R5": (80.0, 32.0, 0),
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"R4": (102.0, 32.0, 0),
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"Q2": (117.0, 33.0, 0),
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"D5": (127.0, 32.0, 0),
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"Q3": (81.0, 52.0, 0), # heatsink space above (tab side)
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"C6": (98.0, 50.0, 0),
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"R6": (119.0, 50.0, 0),
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# ---- panel connector: on the LV/HV boundary, LV pins 4-7 face left, HV pins 1,2,8 right
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"J2": (61.0, 78.0, 90),
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# ---- negative HV (bottom right) ----------------------------------------------
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"Q5": (81.0, 70.0, 0), # heatsink space above (tab side)
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"Q6": (99.0, 70.0, 0),
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"R13": (114.0, 62.0, 0), # 5 W, runs warm: keep clear of caps
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"D7": (74.0, 80.5, 0),
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"D8": (90.0, 79.0, 0),
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"R12": (106.0, 79.0, 0),
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"C8": (122.0, 79.0, 0),
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"D6": (68.0, 89.0, 0),
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"R10": (82.0, 89.0, 0),
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"R9": (105.0, 89.0, 0),
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"Q4": (120.0, 90.0, 0),
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"R11": (130.0, 89.0, 0),
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"C9": (68.0, 99.0, 0),
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"C7": (92.0, 101.0, 0),
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"R7": (106.0, 99.0, 0),
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"R8": (122.0, 99.0, 0),
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"LED2": (144.0, 99.0, 0),
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"F5": (120.0, 111.0, 0),
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"J7": (70.0, 118.5, 0), # NCH6100HV #2 output
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# ---- mounting holes ------------------------------------------------------------
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"H1": (4.0, 4.0, 0),
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"H2": (W - 4.0, 4.0, 0),
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"H3": (4.0, H - 4.0, 0),
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"H4": (W - 4.0, H - 4.0, 0),
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}
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SILK = [
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# (text, x, y, size, layer)
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("PLASMA DMD PSU rev 0.1", 24.0, 102.0, 1.5, "F.SilkS"),
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("J1 12V IN", 13.5, 13.6, 1.0, "F.SilkS"),
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("J3 MINI560", 31.6, 13.6, 1.0, "F.SilkS"),
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("J8 ESP32", 52.1, 13.6, 1.0, "F.SilkS"),
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("J5 HV MOD 1", 71.1, 13.6, 1.0, "F.SilkS"),
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("J4 RELAY MODULE", 21.2, 111.2, 1.0, "F.SilkS"),
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("J6 ISO DC-DC IN", 41.5, 111.2, 1.0, "F.SilkS"),
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("J7 HV MOD 2 OUT", 72.5, 111.2, 1.0, "F.SilkS"),
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("J2 PANEL", 61.0, 44.0, 1.0, "F.SilkS"),
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("DANGER", 158.0, 38.0, 2.0, "F.SilkS"),
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("HIGH VOLTAGE", 158.0, 42.0, 1.6, "F.SilkS"),
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("up to 220V", 158.0, 45.5, 1.2, "F.SilkS"),
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("DANGER HIGH VOLTAGE", 152.0, 70.0, 1.6, "B.SilkS"),
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]
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def mm(v):
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return pcbnew.FromMM(v)
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def pt(x, y):
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return pcbnew.VECTOR2I(mm(OX + x), mm(OY + y))
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FP_DIR = Path(pcbnew.__file__).parents[3] / "share/kicad/footprints" # <KiCad>/10.0/share/...
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def schematic_footprints():
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"""ref -> footprint lib id, read from the schematic."""
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import re
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text = (HERE / "plasma_dmd_psu.kicad_sch").read_text(encoding="utf-8")
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out = {}
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for m in re.finditer(r'\(property "Reference" "([^"]+)".*?\(property "Footprint" "([^"]*)"', text, re.S):
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out[m.group(1)] = m.group(2)
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return out
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def sync_footprints(board):
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"""Swap footprints whose library id no longer matches the schematic (keeps ref, value, nets, link)."""
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wanted = schematic_footprints()
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for old in list(board.GetFootprints()):
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ref = old.GetReference()
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fpid = wanted.get(ref)
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if not fpid or fpid == old.GetFPIDAsString():
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continue
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lib, name = fpid.split(":")
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new = pcbnew.FootprintLoad(str(FP_DIR / f"{lib}.pretty"), name)
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new.SetFPID(pcbnew.LIB_ID(lib, name))
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new.SetReference(ref)
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new.SetValue(old.GetValue())
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new.SetPath(old.GetPath())
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new.SetSheetname(old.GetSheetname())
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new.SetSheetfile(old.GetSheetfile())
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nets = {p.GetNumber(): p.GetNet() for p in old.Pads()}
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board.Add(new)
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for p in new.Pads():
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if p.GetNumber() in nets:
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p.SetNet(nets[p.GetNumber()])
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new.SetPosition(old.GetPosition())
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board.Delete(old)
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print("swapped", ref, "->", fpid)
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def main():
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board = pcbnew.LoadBoard(str(BOARD))
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sync_footprints(board)
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# clean previous layout output (outline, our silkscreen, tracks, vias, zones)
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for d in list(board.GetDrawings()):
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if d.GetLayer() in (pcbnew.Edge_Cuts, pcbnew.F_SilkS, pcbnew.B_SilkS):
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board.Delete(d)
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for getter in (board.GetTracks, board.Zones):
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try:
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items = list(getter())
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except TypeError: # SWIG returns a bare object when the list is empty
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items = []
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for it in items:
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board.Delete(it)
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fps = {f.GetReference(): f for f in board.GetFootprints()}
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missing = set(fps) - set(PLACE)
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extra = set(PLACE) - set(fps)
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if missing or extra:
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raise SystemExit(f"placement table mismatch: missing {missing}, unknown {extra}")
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for ref, (x, y, rot) in PLACE.items():
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f = fps[ref]
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if f.IsFlipped():
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f.Flip(f.GetPosition(), False)
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f.SetOrientationDegrees(rot)
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f.SetPosition(pt(x, y))
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f.SetLocked(ref.startswith(("J", "H")))
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if ref.startswith(("J", "H")):
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f.Reference().SetVisible(False) # connectors are labelled by the SILK texts
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# board outline with 2 mm corner radius
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r = 2.0
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def seg(x1, y1, x2, y2):
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s = pcbnew.PCB_SHAPE(board, pcbnew.SHAPE_T_SEGMENT)
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s.SetStart(pt(x1, y1)); s.SetEnd(pt(x2, y2))
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s.SetLayer(pcbnew.Edge_Cuts); s.SetWidth(mm(0.1)); board.Add(s)
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def arc(cx, cy, sx, sy, ang):
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a = pcbnew.PCB_SHAPE(board, pcbnew.SHAPE_T_ARC)
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a.SetCenter(pt(cx, cy)); a.SetStart(pt(sx, sy)); a.SetArcAngleAndEnd(pcbnew.EDA_ANGLE(ang, pcbnew.DEGREES_T))
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a.SetLayer(pcbnew.Edge_Cuts); a.SetWidth(mm(0.1)); board.Add(a)
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seg(r, 0, W - r, 0); seg(W, r, W, H - r); seg(W - r, H, r, H); seg(0, H - r, 0, r)
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arc(r, r, 0, r, 90); arc(W - r, r, W - r, 0, 90); arc(W - r, H - r, W, H - r, 90); arc(r, H - r, r, H, 90)
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# HV boundary: dashed line on silkscreen (gap where the panel connector J2 straddles it)
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y = 15.0
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while y < H - 3:
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if 42.0 < y < 84.0:
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y += 3.5
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continue
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s = pcbnew.PCB_SHAPE(board, pcbnew.SHAPE_T_SEGMENT)
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s.SetStart(pt(HV_X, y)); s.SetEnd(pt(HV_X, min(y + 2.0, H - 3)))
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s.SetLayer(pcbnew.F_SilkS); s.SetWidth(mm(0.3)); board.Add(s)
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y += 3.5
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for text, x, ty, size, layer in SILK:
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t = pcbnew.PCB_TEXT(board)
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t.SetText(text); t.SetPosition(pt(x, ty))
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t.SetTextSize(pcbnew.VECTOR2I(mm(size), mm(size))); t.SetTextThickness(mm(size * 0.15))
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t.SetLayer(board.GetLayerID(layer))
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if layer.startswith("B."):
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t.SetMirrored(True)
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board.Add(t)
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board.Save(str(BOARD))
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# report pad positions of rotated connectors so orientation can be checked
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for ref in ("J2", "J4", "J6", "J7"):
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f = fps[ref]
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print(ref, [(p.GetNumber(), round(pcbnew.ToMM(p.GetPosition().x) - OX, 2),
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round(pcbnew.ToMM(p.GetPosition().y) - OY, 2)) for p in f.Pads()])
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print("placed", len(PLACE), "footprints")
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if __name__ == "__main__":
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main()
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