Add routed PSU carrier board layout (rev 0.1)

- Placement script (layout_pcb.py): LV left, HV right, panel connector on the boundary, terminal blocks on the edges, heatsink space for the TO-220s - Freerouting-based routing script (route_pcb.py) that routes with oversized tracks/vias and shrinks them, giving 3 mm HV-to-LV and 1.3 mm HV-to-HV - Custom DRC rules (plasma_dmd_psu.kicad_dru) with documented exceptions - Wide TO-92 footprints; schematic generator now keeps symbol UUIDs - DRC: 0 violations, 0 unconnected pads, schematic parity OK Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-24 02:58:35 +02:00
1 parent dbc1f0041f
commit 28c666506e
@@ -42,24 +42,71 @@ stop using the generator once you start editing the schematic in KiCad.

 | Class | Nets | Clearance | Track |
 |---|---|---|---|
-| HV | +90V_RAW, +65V, −130V_RAW, −112V, −100V, HVP/HVN_MOD and all regulator internals | **3.0 mm** | 0.6 mm |
+| HV | +90V_RAW, +65V, −130V_RAW, −112V, −100V, HVP/HVN_MOD and all regulator internals | 1.3 mm (3.0 mm to LV via custom rules) | 0.6 mm |
 | Power | GND, +12V*, +5V, +12V_PANEL | 0.3 mm | 1.0 mm |
-| Default | Watchdog signals | 0.25 mm | 0.4 mm |
+| Default | Watchdog signals, LED cathode/anode nodes | 0.25 mm | 0.4 mm |

-## Making the PCB
+## PCB (rev 0.1)

-1. Open the PCB editor and choose **Tools → Update PCB from Schematic** (F8). All footprints arrive with ratsnest.
-2. Draw the board outline on `Edge.Cuts`.
-3. Placement tips:
-   - Keep the HV area (J5/J7, F4/F5, regulator, J2) on one side and the 12 V/5 V/watchdog on the other.
-   - Leave room for TO-220 heatsinks on Q3, Q5 and Q6. R13 (5 W) runs warm.
-   - Consider routed slots between the HV and low-voltage areas.
-4. Run DRC. The HV class enforces 3 mm to everything.
+![Top view](pcb-top.png)
+
+The board is 170 × 125 mm, 2 layers, with 4 × M3 holes. It is fully routed with a bottom-layer GND pour.
+DRC is clean: 0 violations, 0 unconnected pads, schematic parity OK.
+
+- **Left: low voltage.** 12 V input, Mini560, ESP32 watchdog, relay, F1–F3.
+- **Right: high voltage.** +65 V regulator at the top, −112/−100 V regulator at the bottom.
+  A dashed silkscreen line marks the boundary, with DANGER text on both sides.
+- **J2 (panel)** straddles the boundary. Its LV pins (GND, +5V, +12V) leave towards the left, its HV pins towards the right.
+- **Terminal blocks** sit on the top and bottom edges, with wire entries facing outwards.
+- **Heatsink space** is left above Q3, Q5 and Q6.
+
+> ⚠️ **The TO-220 tabs are live.** Q3's tab is at +90 V, Q5's at −130 V and Q6's at Q6_C.
+> Give each transistor its own heatsink, keep the heatsinks apart, and don't let them touch anything.
+
+### Clearance rules
+
+The classes are in the project, and the custom rules are in `plasma_dmd_psu.kicad_dru`. Later rules win.
+
+| Between | Clearance | Why |
+|---|---|---|
+| HV and LV (GND, 12 V, 5 V, watchdog) | **3.0 mm** | Keeps HV well away from the touchable side |
+| HV and HV | 1.3 mm | IPC-2221 B2 needs 1.25 mm up to 300 V |
+| HV and LV, next to a connector pin | 1.8 mm | Fixed pin pitch of J2/J5/J7 |
+| HV and HV, next to a transistor pin | 1.0 mm | TO-220 pin escape; same-polarity nets only |
+| Pins inside one connector / transistor / HV electrolytic | 0.75 / 0.6 / 2.5 mm | Fixed footprint pitch |
+
+### Regenerating the board
+
+The layout is produced by two scripts, run with KiCad's Python while KiCad is closed:
+
+```bash
+"C:/Users/patri/AppData/Local/Programs/KiCad/10.0/bin/python.exe" hardware/kicad/layout_pcb.py
+"C:/Users/patri/AppData/Local/Programs/KiCad/10.0/bin/python.exe" hardware/kicad/route_pcb.py
+```
+
+- `layout_pcb.py` places every footprint from its `PLACE` table and draws the outline, holes and silkscreen.
+  It also swaps in any footprint that changed in the schematic. **It deletes all tracks and zones.**
+- `route_pcb.py` autoroutes with Freerouting (`tools/freerouting/`, needs Java 25):
+  - It routes with oversized tracks and vias, then shrinks them to their real width. This turns
+    the router's smaller clearances into 3 mm for HV to LV and 1.3 mm for HV to HV.
+  - It adds fixed escape stubs on J2 and the GND pour.
+  - Run DRC afterwards: `kicad-cli pcb drc --schematic-parity --refill-zones hardware/kicad/plasma_dmd_psu.kicad_pcb`.
+
+Once you start hand-editing the board in KiCad, stop running these scripts. They would overwrite your edits.
+
+### Before ordering
+
+- [ ] Check every footprint against the parts you actually buy: fuse holders, the 12.5 mm caps, the R13 5 W size, and the terminal block pitch.
+- [ ] Map J2 to your panel's power connector. The current order follows the Stern CN2 connector.
+- [ ] Check heatsink size and clearance for Q3/Q5/Q6.
+- [ ] Consider conformal coating on the HV side.
+- [ ] Get a second pair of eyes on the HV layout.

 ## Verified so far

 - The schematic loads in KiCad 10.0.6, and ERC reports 0 violations.
 - `check_netlist.py`: all 122 pins sit on the intended nets (31 nets).
+- PCB DRC with schematic parity: 0 violations, 0 unconnected pads.
 - All symbols and footprints come from the KiCad 10 standard libraries.
 - Transistor pinouts match the footprints: MJE15030/31 are B-C-E (TO-220); MPSA42/92 are E-B-C (TO-92); 2N7000 is S-G-D.