mangavalkandClaude Opus 5.5 df78b5e72c Fix VCLK at half rate; chunk the DMA stream; cycle test images ...

PCNT measurement showed I2S0 BCK (VCLK) rising once per two bytes in 8-bit
LCD mode, so the panel saw every other byte. Each VCLK is now two identical
bytes at a 10 MHz byte rate (VCLK 5 MHz). The doubled ~142 KB stream is
allocated as 38 per-descriptor chunks.

The test sketch now cycles through 12 labelled test images.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

2026-10-18 18:12:41 +02:00

..

src

Fix VCLK at half rate; chunk the DMA stream; cycle test images

2026-10-18 18:12:41 +02:00

library.json

Set up PlatformIO project for EL512.256-H on ESP32

2026-10-05 21:00:42 +02:00