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mangavalkandClaude Opus 5.5 873bdcd23e Set up PlatformIO project for EL512.256-H on ESP32

PlatformIO skeleton (esp32dev, Arduino, Adafruit GFX) with a local EL512
library: EL512Panel (1 bpp framebuffer, two-bit-mode row encoder, I2S DMA
refresh stub) and EL512_GFX (Adafruit_GFX subclass). Adds a test sketch,
pin map, README with wiring and timing, and moves the datasheet to
docs/datasheet/.

Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>

2026-10-05 21:00:42 +02:00

datasheet

Set up PlatformIO project for EL512.256-H on ESP32

2026-10-05 21:00:42 +02:00

README.md

Set up PlatformIO project for EL512.256-H on ESP32

2026-10-05 21:00:42 +02:00

README.md

Notes

Plan: https://claude.ai/code/artifact/3b9eda11-a87e-4eea-bbb9-e6454e558991
Datasheet: datasheet/EL512.256-H3 FRB.pdf

Approach

I2S0 in 8-bit parallel (LCD) mode with a circular DMA descriptor chain. Each DMA byte is one VCLK period:

Bit	Signal
0	VID (even columns)
1	TVID (odd columns)
2	HS
3	VS

The I2S clock output drives VCLK. ENABLE (GPIO 25) and _LOWPWR (GPIO 26) are plain GPIO.

From the datasheet

Two-bit parallel mode is selected with the mode jumper OFF. Even columns on VID, odd columns on TVID; 256 VCLKs per row.
VCLK is active on the rising edge and should be kept running.
HS is high while the pixels of a row are clocked in. The number of VCLKs during HS high should be even.
The topmost row is the first HS high time ending after the rising edge of VS.

Open items

Implement EL512Panel::startI2S() (I2S0 LCD mode, clock dividers for 5 MHz, GPIO matrix routing, circular lldesc_t chain).
Handle the 8-bit LCD-mode byte-pair swap in encodeRow().
Check VS/HS setup and hold (T4/T5) and VCLK polarity on a scope.
Tear-free updates (double buffer or swap at VS).
Unit test for encodeRow().