Public Access
mangavalkandClaude Opus 5.5
3640c7fb3f
startI2S() sets up I2S0 in 8-bit parallel (LCD) mode at 5 MHz (PLL_D2 160 MHz / 32, BCK div 1), routes stream bits 0..3 to VID/TVID/HS/VS via I2S0O_DATA_OUT16+n and BCK to VCLK, and loops DMA over an 18-descriptor chain of whole lines. stopI2S() stops TX, returns the pins to GPIO low and frees the chain. encodeRow() now stores clock c at c ^ 2 to match the 8-bit mode byte order (bytes 2, 3, 0, 1 per word, as in bitluni's ESP32Lib). Builds with no warnings; not yet checked on hardware. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
23 lines
709 B
C++
23 lines
709 B
C++
// Pin map for the EL512.256-H panel on an ESP-WROOM-32 (esp32dev).
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//
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// VCLK, VID, TVID, HS and VS are driven by I2S0 in 8-bit parallel (LCD) mode,
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// so their levels come from a DMA byte stream. ENABLE and _LOWPWR are plain GPIO.
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#pragma once
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#include <stdint.h>
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namespace el512pins {
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// I2S-driven signals
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constexpr int8_t VCLK = 18; // I2S0 BCK out -> panel VCLK
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constexpr int8_t VID = 19; // byte bit 0
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constexpr int8_t TVID = 21; // byte bit 1
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constexpr int8_t HS = 22; // byte bit 2
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constexpr int8_t VS = 23; // byte bit 3
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// Static control lines
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constexpr int8_t ENABLE = 25; // high = display enabled
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constexpr int8_t LOWPWR_N = 26; // _LOWPWR, active low
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} // namespace el512pins
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