diff --git a/docs/README.md b/docs/README.md
index 6585913..0d73aa5 100644
--- a/docs/README.md
+++ b/docs/README.md
@@ -75,9 +75,11 @@ Hardware checks:
       scope (HS 256 clocks high / 16 low, T6-T8).
 - [x] VCLK edge phase: with `INVERT_VCLK = false` the image jittered (rising edge on
       the byte-pair boundary); `true` puts it mid-pair and the jitter is gone.
-- [ ] "row stripes" test image: brightness drifts in slow waves. Unexplained;
-      suspected beat between the alternating full/empty row load and the panel's
-      DC/DC converter or row drive.
+- [x] "row stripes" test image: brightness drifts in slow waves. Panel behaviour,
+      not the signal: unchanged at 73.7 Hz (260 clocks/row) vs 70.4 Hz, on a 15 V 4 A
+      Vcc2 supply, while the checkerboard (same average load, spread within each row)
+      and all other images are stable. Attributed to the panel's drive reacting to
+      whole rows alternating fully on / fully off; kept 272 clocks/row.
 - [ ] Confirm the `^ 2` byte order. HS edges sit on word boundaries, so a wrong order
       does not show on HS; on the panel it shuffles pixels in groups of 8 (a 1-pixel
       line at x = 0 lands at x = 4).