Fix VCLK at half rate; chunk the DMA stream; cycle test images

PCNT measurement showed I2S0 BCK (VCLK) rising once per two bytes in 8-bit
LCD mode, so the panel saw every other byte. Each VCLK is now two identical
bytes at a 10 MHz byte rate (VCLK 5 MHz). The doubled ~142 KB stream is
allocated as 38 per-descriptor chunks.

The test sketch now cycles through 12 labelled test images.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

test/README

@@ -2,8 +2,8 @@ Unit tests (PlatformIO Unit Testing / Unity) go here.
 
 Planned first test: EL512Panel::encodeRow() - check that HS is high for exactly
 256 clocks per visible row, VS appears only on the last blanking line, that x = 0
-(datasheet column 1, odd) lands on TVID and x = 1 on VID, and that clock c is
-stored at index c ^ 2 (8-bit I2S byte order).
+(datasheet column 1, odd) lands on TVID and x = 1 on VID, and that each clock is
+two identical bytes with stream byte i stored at index i ^ 2 (8-bit I2S byte order).
 
 Run with:  pio test -e esp32dev