Fix VCLK at half rate; chunk the DMA stream; cycle test images

PCNT measurement showed I2S0 BCK (VCLK) rising once per two bytes in 8-bit
LCD mode, so the panel saw every other byte. Each VCLK is now two identical
bytes at a 10 MHz byte rate (VCLK 5 MHz). The doubled ~142 KB stream is
allocated as 38 per-descriptor chunks.

The test sketch now cycles through 12 labelled test images.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

README.md

@@ -9,8 +9,8 @@ peripheral in 8-bit parallel (LCD) mode streams a precomputed frame from DMA, so
 CPU is free while the panel refreshes.
 
 **Status:** framebuffer, GFX layer, row encoder and I2S/DMA refresh are implemented and
-build cleanly; the signal timing has not yet been checked on hardware. Updates are not
-yet tear-free.
+run on hardware: the panel shows a correct image (VCLK 5 MHz, HS and VS checked with
+the ESP32's PCNT). Updates are not yet tear-free.
 
 ## Hardware
 
@@ -68,7 +68,7 @@ truth; if anything here disagrees with it, the datasheet wins.
 ```
 platformio.ini        build config (esp32dev, Arduino, Adafruit GFX)
 include/pins.h        pin map
-src/main.cpp          test sketch: test pattern + text
+src/main.cpp          test sketch: cycles through test images
 lib/EL512/            local library
   src/EL512Panel.*    framebuffer, row encoder, I2S DMA refresh
   src/EL512_GFX.*     Adafruit_GFX subclass