Project check against the datasheet; fix column parity

The datasheet numbers columns from 1 (Fig. 3: "row 1", "Last pixel
(512 / 256)") and puts odd columns on TVID, so x = 0 (column 1) now
goes to TVID and x = 1 to VID; the encoder had them swapped.

README wiring now lists the J1/J2 pins and power rails from Table 1,
the 5 V buffer, and a pull-down on ENABLE so the panel stays off while
the ESP32 boots without VCLK. encodeRow() documents its T4/T5 margins.
docs/README.md open items are regrouped into done, hardware checks and
software work. main.cpp counts seconds, not frames.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

docs/README.md

@@ -35,6 +35,8 @@ other doc, comment or the plan.
 - Two-bit parallel mode is selected by removing jumper 2 (DCONFIG) of pin strip PS1
   (Table 3; factory default has jumpers 1 and 2 fitted). Even columns on VID, odd
   columns on TVID, numbered from the left as seen by the viewer; 256 VCLKs per row.
+  The datasheet numbers from 1 (Fig. 3: "row 1", "Last pixel (512 / 256)"), so the
+  leftmost pixel, x = 0 in the code, is column 1 and goes on TVID.
 - VCLK is active on the rising edge and should be kept running.
 - HS envelopes the pixels of a row: the visible pixels are the last 512 (two-bit mode:
   last 256 clocks) before HS falls. The number of VCLKs during HS high should be even.
@@ -49,14 +51,37 @@ other doc, comment or the plan.
 
 ## Open items
 
-- [x] Implement `EL512Panel::startI2S()` (I2S0 LCD mode, clock dividers for 5 MHz,
+Done:
+
+- [x] Implement `EL512Panel::startI2S()` (I2S0 LCD mode, 5 MHz from PLL_D2 / 32,
       GPIO matrix routing, circular `lldesc_t` chain).
-- [x] Handle the 8-bit LCD-mode byte-pair swap in `encodeRow()`.
-- [ ] Check on a scope: VCLK is 5 MHz on GPIO 18, HS is 256 clocks high / 16 low
-      (54.4 us period), VS is one line high per 14.2 ms frame, data changes on the
-      falling VCLK edge, VS/HS setup and hold (T4/T5). Unconfirmed until then: the
-      DATA_OUT16 base and the `^ 2` byte order. HS edges sit on word boundaries, so a
-      wrong order does not show on HS; on the panel it shuffles pixels in groups of 8
-      (a 1-pixel line at x = 0 lands at x = 4).
-- [ ] Tear-free updates (double buffer or swap at VS).
-- [ ] Unit test for `encodeRow()`.
+- [x] Handle the 8-bit LCD-mode byte-pair swap in `encodeRow()` (clock c at `c ^ 2`).
+- [x] Map x = 0 (datasheet column 1, odd) to TVID, not VID.
+
+Hardware checks (need the panel and a scope or logic analyser):
+
+- [ ] Self test first (Table 3): remove PS1 jumper 1, power up; all pixels except the
+      first half of the top row should light. Refit jumper 1, remove jumper 2.
+- [ ] Scope: VCLK 5 MHz on GPIO 18; HS 256 clocks high / 16 low (54.4 µs, T6-T8);
+      VS one line high per 14.2 ms frame (70.4 Hz); data changing on the falling VCLK
+      edge with >= 8 ns setup/hold (Table 6); T1 220.8 µs, T4/T5 as in `encodeRow()`.
+      If data changes on the rising edge, set `INVERT_VCLK`.
+- [ ] Confirm the I2S0 data signal base (`I2S0O_DATA_OUT16_IDX`): if GPIO 19/21/22/23
+      stay idle, try `I2S0O_DATA_OUT8_IDX`.
+- [ ] Confirm the `^ 2` byte order. HS edges sit on word boundaries, so a wrong order
+      does not show on HS; on the panel it shuffles pixels in groups of 8 (a 1-pixel
+      line at x = 0 lands at x = 4).
+- [ ] Confirm the column parity: the checkerboard in `main.cpp` must look identical to
+      the framebuffer, and the left border must sit on the panel's first column.
+- [ ] Add the 5 V buffer (74HCT245/74AHCT541) and a pull-down on ENABLE so the panel
+      stays off while the ESP32 boots without VCLK (Table 1: ENABLE pulled high
+      internally; Table 5 note 3: VCLK should be kept running).
+
+Software:
+
+- [ ] Tear-free updates: `show()` rewrites the stream while DMA reads it. Encode into
+      a second buffer and swap descriptors at the per-frame EOF, or encode only during
+      vertical blanking.
+- [ ] Unit test for `encodeRow()` (see `test/README`).
+- [ ] The 71 KB stream is one contiguous DMA allocation; with Wi-Fi on it may not fit.
+      Fallback: per-line buffers or a line ring refilled from the EOF interrupt.