Project check against the datasheet; fix column parity

The datasheet numbers columns from 1 (Fig. 3: "row 1", "Last pixel
(512 / 256)") and puts odd columns on TVID, so x = 0 (column 1) now
goes to TVID and x = 1 to VID; the encoder had them swapped.

README wiring now lists the J1/J2 pins and power rails from Table 1,
the 5 V buffer, and a pull-down on ENABLE so the panel stays off while
the ESP32 boots without VCLK. encodeRow() documents its T4/T5 margins.
docs/README.md open items are regrouped into done, hardware checks and
software work. main.cpp counts seconds, not frames.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

README.md

@@ -22,16 +22,29 @@ yet tear-free.
 
 ## Wiring
 
-| Panel signal | Function                                | ESP32 GPIO | DMA byte bit |
-|--------------|-----------------------------------------|-----------:|-------------:|
-| VCLK         | Video clock (rising edge)               | 18         | I2S0 BCK     |
-| VID          | Pixel data, even columns                | 19         | 0            |
-| TVID         | Pixel data, odd columns (two-bit mode)  | 21         | 1            |
-| HS           | Horizontal sync                         | 22         | 2            |
-| VS           | Vertical sync                           | 23         | 3            |
-| ENABLE       | Display enable                          | 25         | —            |
-| _LOWPWR      | Low-power mode (active low)             | 26         | —            |
-| GND          | Ground                                  | GND        | —            |
+| Panel signal | Panel pin (Table 1) | Function                                     | ESP32 GPIO | DMA byte bit |
+|--------------|---------------------|----------------------------------------------|-----------:|-------------:|
+| VCLK         | J1-13               | Video clock, data latched on rising edge     | 18         | I2S0 BCK     |
+| VID          | J1-15               | Pixel data, even columns (x = 1, 3, …)       | 19         | 0            |
+| TVID         | J1-7                | Pixel data, odd columns (x = 0, 2, …)        | 21         | 1            |
+| HS           | J1-11               | Horizontal sync                              | 22         | 2            |
+| VS           | J1-9                | Vertical sync (rising edge used)             | 23         | 3            |
+| ENABLE       | J2-6                | Display enable, low = off                    | 25         | —            |
+| _LOWPWR      | J2-5                | Low-power mode, low = on                     | 26         | —            |
+| GND          | J1-6, 8, 10, 12, 14, 16 | Signal return                            | GND        | —            |
+
+The datasheet numbers columns 1 to 512 from the left; x in the code is 0-based, so
+x = 0 is column 1 (odd, TVID).
+
+Power (Table 1, Table 4): Vcc1 +5 V logic on J1-3, 4 (4.75–5.25 V, 0.2 A max);
+Vcc2 +11…+30 V on J1-1, 2 (0.9 A max at 12 V). J1-5 is reserved: do not connect.
+
+The panel inputs are HCT compatible with internal pull-ups of unstated voltage, and the
+ESP32 is not 5 V tolerant, so drive them through a 74HCT245 or 74AHCT541 powered from
+5 V (see the plan). ENABLE is pulled high inside the panel, so the panel scans while
+the ESP32 is still booting and VCLK is not running yet; add a pull-down (for example
+10 kΩ) on the buffer's ENABLE input so the panel stays off until `begin()` starts the
+stream. Keep the cable under 300 mm, or add 47 Ω series resistors for up to 2 m.
 
 The pin map lives in [include/pins.h](include/pins.h).