mangavalk/planar-EL512.256-H
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Align docs with the EL512.256-H datasheet

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The datasheet (docs/datasheet, Planar 020-0354-00A) is now stated as the
source of truth. Two-bit mode is PS1 jumper 2 (DCONFIG) removed
(Table 3), not a generic "mode jumper". The README timing table now lists
the Table 5/6 limits beside our values, and the notes add T1-T8, the
8 ns setup/hold from Figure 4 and the input levels from Table 4.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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mangavalkandClaude Opus 5.5 committed 2026-10-05 21:13:36 +02:00
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commit 37d5bcc1f8
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lib/EL512/src/EL512Panel.h
+1 -1
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@@ -10,7 +10,7 @@
// byte bit 3 = VS (marks the top row)
// I2S BCK -> VCLK (panel samples data on the rising edge)
//
// Panel in two-bit parallel mode (jumper OFF, see datasheet), 5 MHz VCLK:
// Panel in two-bit parallel mode (PS1 jumper 2 removed, datasheet Table 3), 5 MHz VCLK:
// 272 clocks per row (256 data + 16 blanking), 261 rows per frame
// (256 visible + 5 blanking) -> 5e6 / (272 * 261) ~= 70.4 Hz.
//