Align docs with the EL512.256-H datasheet

The datasheet (docs/datasheet, Planar 020-0354-00A) is now stated as the
source of truth. Two-bit mode is PS1 jumper 2 (DCONFIG) removed
(Table 3), not a generic "mode jumper". The README timing table now lists
the Table 5/6 limits beside our values, and the notes add T1-T8, the
8 ns setup/hold from Figure 4 and the input levels from Table 4.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

docs/README.md

@@ -29,12 +29,23 @@ I2S0 setup (`EL512Panel::startI2S()`), following bitluni's ESP32Lib 8-bit mode:
 
 ## From the datasheet
 
-- Two-bit parallel mode is selected with the mode jumper OFF. Even columns on VID,
-  odd columns on TVID; 256 VCLKs per row.
+The datasheet is the source of truth for everything in this section and wins over any
+other doc, comment or the plan.
+
+- Two-bit parallel mode is selected by removing jumper 2 (DCONFIG) of pin strip PS1
+  (Table 3; factory default has jumpers 1 and 2 fitted). Even columns on VID, odd
+  columns on TVID, numbered from the left as seen by the viewer; 256 VCLKs per row.
 - VCLK is active on the rising edge and should be kept running.
-- HS is high while the pixels of a row are clocked in. The number of VCLKs during HS
-  high should be even.
-- The topmost row is the first HS high time ending after the rising edge of VS.
+- HS envelopes the pixels of a row: the visible pixels are the last 512 (two-bit mode:
+  last 256 clocks) before HS falls. The number of VCLKs during HS high should be even.
+- The topmost row is the first HS high time ending after the rising edge of VS. Only
+  the rising edge of VS is used; VS high/low time is at least 1 VCLK (T2).
+- Table 5: front porch T1 >= 100 µs, HS setup to VS T4 >= 1 VCLK, HS hold from VS
+  T5 >= 3 µs, HS low T6 >= 4 VCLK, HS period T8 >= 50 µs, VS 70 Hz typ / 75 Hz max.
+- Figure 4 / Table 6: VID, TVID, HS and VS need 8 ns setup and 8 ns hold around the
+  rising VCLK edge; VCLK period >= 33 ns (30 MHz max).
+- Inputs are HCT compatible with pull-ups (Table 4: high >= 2 V, low <= 0.8 V,
+  abs. max Vcc1 + 0.5 V). ENABLE and _LOWPWR are on J2 and pulled high internally.
 
 ## Open items