Align docs with the EL512.256-H datasheet

The datasheet (docs/datasheet, Planar 020-0354-00A) is now stated as the
source of truth. Two-bit mode is PS1 jumper 2 (DCONFIG) removed
(Table 3), not a generic "mode jumper". The README timing table now lists
the Table 5/6 limits beside our values, and the notes add T1-T8, the
8 ns setup/hold from Figure 4 and the input levels from Table 4.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

README.md

@@ -15,7 +15,8 @@ yet tear-free.
 ## Hardware
 
 - ESP-WROOM-32 dev board (`esp32dev`)
-- Planar EL512.256-H, configured for **two-bit parallel mode** (mode jumper OFF, see datasheet)
+- Planar EL512.256-H, configured for **two-bit parallel mode**: jumper 2 (DCONFIG) of pin
+  strip PS1 removed, jumper 1 (SELFTST) fitted (datasheet Table 3)
 - Datasheet: [docs/datasheet/EL512.256-H3 FRB.pdf](docs/datasheet/EL512.256-H3%20FRB.pdf)
 - Check the panel's logic-level and supply requirements in the datasheet before wiring.
 
@@ -36,12 +37,18 @@ The pin map lives in [include/pins.h](include/pins.h).
 
 ## Timing
 
-| Parameter            | Value                                   |
-|----------------------|-----------------------------------------|
-| Pixel clock (VCLK)   | 5 MHz, 2 pixels per clock               |
-| Clocks per row       | 272 (256 data + 16 blanking)            |
-| Lines per frame      | 261 (256 visible + 5 blanking)          |
-| Refresh              | 5 MHz / (272 × 261) ≈ 70.4 Hz           |
+| Parameter            | Value                                   | Datasheet limit (Tables 5, 6)   |
+|----------------------|-----------------------------------------|---------------------------------|
+| Pixel clock (VCLK)   | 5 MHz, 2 pixels per clock               | 30 MHz max, keep running        |
+| HS high (T7)         | 256 clocks                              | 256 in two-bit mode, even       |
+| HS low (T6)          | 16 clocks                               | 4 clocks min                    |
+| HS period (T8)       | 272 clocks = 54.4 µs                    | 50 µs min                       |
+| Lines per frame      | 261 (256 visible + 5 blanking)          | 256 rows + T1                   |
+| Front porch (T1)     | 220.8 µs (last row end to VS rise)      | 100 µs min                      |
+| Refresh              | 5 MHz / (272 × 261) ≈ 70.4 Hz           | 70 Hz typ, 75 Hz max            |
+
+The datasheet ([docs/datasheet/](docs/datasheet/EL512.256-H3%20FRB.pdf)) is the source of
+truth; if anything here disagrees with it, the datasheet wins.
 
 ## Layout