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Implement I2S0 8-bit LCD-mode DMA refresh
startI2S() sets up I2S0 in 8-bit parallel (LCD) mode at 5 MHz (PLL_D2 160 MHz / 32, BCK div 1), routes stream bits 0..3 to VID/TVID/HS/VS via I2S0O_DATA_OUT16+n and BCK to VCLK, and loops DMA over an 18-descriptor chain of whole lines. stopI2S() stops TX, returns the pins to GPIO low and frees the chain. encodeRow() now stores clock c at c ^ 2 to match the 8-bit mode byte order (bytes 2, 3, 0, 1 per word, as in bitluni's ESP32Lib). Builds with no warnings; not yet checked on hardware. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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@@ -8,8 +8,9 @@ The panel has no frame memory and needs a continuous video stream. The ESP32's I
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peripheral in 8-bit parallel (LCD) mode streams a precomputed frame from DMA, so the
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CPU is free while the panel refreshes.
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**Status:** project skeleton. Framebuffer, GFX layer and row encoder are in place; the
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I2S/DMA start-up (`EL512Panel::startI2S()`) is still a stub.
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**Status:** framebuffer, GFX layer, row encoder and I2S/DMA refresh are implemented and
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build cleanly; the signal timing has not yet been checked on hardware. Updates are not
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yet tear-free.
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## Hardware
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@@ -22,7 +23,7 @@ I2S/DMA start-up (`EL512Panel::startI2S()`) is still a stub.
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| Panel signal | Function | ESP32 GPIO | DMA byte bit |
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|--------------|-----------------------------------------|-----------:|-------------:|
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| VCLK | Video clock (rising edge) | 18 | I2S clock |
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| VCLK | Video clock (rising edge) | 18 | I2S0 BCK |
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| VID | Pixel data, even columns | 19 | 0 |
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| TVID | Pixel data, odd columns (two-bit mode) | 21 | 1 |
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| HS | Horizontal sync | 22 | 2 |
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@@ -49,7 +50,7 @@ platformio.ini build config (esp32dev, Arduino, Adafruit GFX)
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include/pins.h pin map
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src/main.cpp test sketch: test pattern + text
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lib/EL512/ local library
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src/EL512Panel.* framebuffer, row encoder, I2S DMA refresh (stub)
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src/EL512Panel.* framebuffer, row encoder, I2S DMA refresh
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src/EL512_GFX.* Adafruit_GFX subclass
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test/ unit tests (placeholder)
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docs/ datasheet and notes
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