Plasma-DMD/hardware/kicad

KiCad project: PSU carrier board

Open plasma_dmd_psu.kicad_pro in KiCad 10.

The board carries the fuses, the HV watchdog, both regulators (copied from Stern 520-5138-00) and the connectors. The AliExpress modules sit off-board and connect through Phoenix 5.08 mm screw terminals:

Connector	Goes to	Pins
J1	12 V DC brick	+12V, GND
J3	Mini560 5 V buck	IN+, IN−, OUT+, OUT−
J4	Relay module	VCC, GND, IN, COM, NO
J5	NCH6100HV #1 (set 90 V)	VIN, GND, HV+
J6	Isolated DC-DC input	VIN, GND
J7	NCH6100HV #2 (set 130 V) output	HV+ (→ GND), GND (→ −130 V raw)
J8	ESP32	5V, GND, GPIO21 (watchdog)
J2	Panel power, Molex KK-396 8-pin	Stern CN2 order: 1 −112V, 2 −100V, 3 key, 4–5 GND, 6 +5V, 7 +12V (via JP1), 8 +65V

Wire the isolated DC-DC output straight to NCH6100HV #2's input, off-board. Both float at −130 V.

⚠️ J2 pinout is a placeholder. It follows the Stern supply, not necessarily your WPC panel. Map it to your panel before you plug anything in.

Files

File	What
gen_kicad.py	Generates the schematic and the project's net classes from the PARTS table. The source of truth.
check_netlist.py	Exports the netlist with kicad-cli and checks every pin against PARTS
plasma_dmd_psu.kicad_sch	Generated schematic (labels-per-pin style: connectivity is by net label)
plasma_dmd_psu.pdf	Plot of the schematic
plasma_dmd.pretty/, fp-lib-table	Project footprint library (courtyard-less heatsink)
layout_pcb.py, route_pcb.py	Placement and autorouting scripts (see below)
plasma_dmd_psu.kicad_dru	Custom clearance rules

python hardware/kicad/gen_kicad.py
python hardware/kicad/check_netlist.py

Re-running gen_kicad.py overwrites the schematic. Either keep editing PARTS and regenerate, or stop using the generator once you start editing the schematic in KiCad.

Net classes (already in the project)

Class	Nets	Clearance	Track
HV	+90V_RAW, +65V, −130V_RAW, −112V, −100V, HVP/HVN_MOD and all regulator internals	1.3 mm (3.0 mm to LV via custom rules)	0.6 mm
Power3A	+12V_IN, +12V (behind the 3 A fuse F1)	0.3 mm	1.5 mm
Power	GND (plus the bottom pour), +12V_HV/HVP/HVN, +5V, +12V_PANEL	0.3 mm	1.0 mm
Default	Watchdog signals, LED cathode/anode nodes	0.25 mm	0.4 mm

PCB (rev 0.1)

The board is 170 × 125 mm, 2 layers, with 4 × M3 holes. It is fully routed with a bottom-layer GND pour. DRC is clean: 0 violations, 0 unconnected pads, schematic parity OK.

• Left: low voltage. 12 V input, Mini560, ESP32 watchdog, relay, F1–F3.
• Right: high voltage. +65 V regulator at the top, −112/−100 V regulator at the bottom. A dashed silkscreen line marks the boundary, with DANGER text on both sides.
• J2 (panel) straddles the boundary. Its LV pins (GND, +5V, +12V) leave towards the left, its HV pins towards the right.
• Terminal blocks sit on the top and bottom edges, with wire entries facing outwards.
• Heatsinks HS1–HS3 (Aavid 576802B03900G clip-on, about 20 K/W) sit on Q3, Q5 and Q6.

⚠️ The heatsinks are live. Each one clips straight onto its transistor's tab: HS1 is at +90 V, HS2 at −130 V and HS3 at Q6_C. That's why each heatsink's solder pin is on the collector net, so the HV clearance rules also protect it. Never let the heatsinks touch each other or anything else.

Heatsinks

• Footprint: plasma_dmd:Heatsink_AAVID_576802B03900G_NoCourtyard in the project library plasma_dmd.pretty. It's a copy of KiCad's footprint with the courtyard and silkscreen outline removed, because the clip wraps around the transistor and would always overlap its courtyard. The outline is kept on F.Fab, and the footprint is marked "exempt from courtyard requirement".
• Placement: layout_pcb.py places each heatsink relative to its transistor (heatsink_for()), with its tab face on the TO-220 tab.
• Dissipation (estimate): about 1–1.5 W per transistor. Bare TO-220 runs at about 62 K/W (60–90 °C rise); with the heatsink, about 20 K/W (about 30 °C rise).
• Project setting: "PTH inside courtyard" is set to ignore, because each heatsink pin sits just behind its tab, inside the transistor courtyard. Courtyard overlaps are still checked for all other parts.
• Remaining DRC items: the 9 silkscreen warnings are the TO-220 outlines over the heatsink pins. The fab clips silkscreen off pads, so they're harmless.

Current capacity

Track widths follow IPC-2221 for 1 oz outer copper. Currents are estimated from the fuses.

Net	Max current (fuse)	Width	Capacity at 10 °C rise
+12V_IN, +12V	3 A (F1)	1.5 mm	≈ 3.2 A
GND return	3 A	1.0 mm + solid bottom pour on the LV side	well above 3 A
+12V_HV	2 A (F2 + F3)	1.0 mm	≈ 2.4 A
+12V_HVP, +12V_HVN	1 A (F2, F3)	1.0 mm	≈ 2.4 A
+5V	about 1 A (unfused, from the Mini560)	1.0 mm	≈ 2.4 A
HV nets	100 mA (F4, F5)	0.6 mm	≈ 1.7 A (width set by clearance, not current)
Signals	mA	0.4 mm	≈ 1.2 A

The 12 V input path, GND and +5V have no vias.

• Note on F3: if the negative rail ever drew the full 100 mA that F5 allows (about 13 W), the isolated converter plus the boost module would pull more than 1 A at 12 V. That would blow F3. Measure the real HV current at bring-up.
• Note on +5V: the 5 V side isn't fused on its own. Consider a polyfuse (about 1.5 A) if the panel or the ESP32 wiring could short.

Clearance rules

The classes are in the project, and the custom rules are in plasma_dmd_psu.kicad_dru. Later rules win.

Between	Clearance	Why
HV and LV (GND, 12 V, 5 V, watchdog)	3.0 mm	Keeps HV well away from the touchable side
HV and HV	1.3 mm	IPC-2221 B2 needs 1.25 mm up to 300 V
HV and LV, next to a connector pin	1.8 mm	Fixed pin pitch of J2/J5/J7
HV and HV, next to a transistor pin	1.0 mm	TO-220 pin escape; same-polarity nets only
Pins inside one connector / transistor / HV electrolytic	0.75 / 0.6 / 2.5 mm	Fixed footprint pitch

Regenerating the board

The layout is produced by two scripts, run with KiCad's Python while KiCad is closed:

"C:/Users/patri/AppData/Local/Programs/KiCad/10.0/bin/python.exe" hardware/kicad/layout_pcb.py
"C:/Users/patri/AppData/Local/Programs/KiCad/10.0/bin/python.exe" hardware/kicad/route_pcb.py

• layout_pcb.py places every footprint from its PLACE table and draws the outline, holes and silkscreen. It also swaps in any footprint that changed in the schematic. It deletes all tracks and zones.
• route_pcb.py autoroutes with Freerouting (tools/freerouting/, needs Java 25):
  • It routes with oversized tracks and vias, then shrinks them to their real width. This turns the router's smaller clearances into 3 mm for HV to LV and 1.3 mm for HV to HV.
  • It adds fixed escape stubs on J2 and the GND pour.
  • Run DRC afterwards: kicad-cli pcb drc --schematic-parity --refill-zones hardware/kicad/plasma_dmd_psu.kicad_pcb.

Once you start hand-editing the board in KiCad, stop running these scripts. They would overwrite your edits.

Before ordering

• Check every footprint against the parts you actually buy: fuse holders, the 12.5 mm caps, the R13 5 W size, and the terminal block pitch.
• Map J2 to your panel's power connector. The current order follows the Stern CN2 connector.
• Check the heatsink orientation against the Aavid 5768 drawing. KiCad has no 3D model for it, so it isn't visible in the render.
• Consider conformal coating on the HV side.
• Get a second pair of eyes on the HV layout.

Verified so far

• The schematic loads in KiCad 10.0.6, and ERC reports 0 violations.
• check_netlist.py: all 122 pins sit on the intended nets (31 nets).
• PCB DRC with schematic parity: 0 violations, 0 unconnected pads.
• All symbols and footprints come from the KiCad 10 standard libraries.
• Transistor pinouts match the footprints: MJE15030/31 are B-C-E (TO-220); MPSA42/92 are E-B-C (TO-92); 2N7000 is S-G-D.

Not verified: the circuit itself on real hardware, and the module current ratings.