- PCB rev 0.1: Power3A class (1.5 mm) for the 12 V input path, Aavid
clip-on heatsinks on Q3/Q5/Q6 (project footprint library), T-junction
healing and via shrink in the router; DRC 0 errors
- Current-capacity and heatsink documentation
- CLAUDE.md with project decisions, workflow and gotchas
- docs/design-review.md: review of a module-only PSU (rev 0.2) and cost
estimate
- Project paused for budget and safety reasons
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
- Placement script (layout_pcb.py): LV left, HV right, panel connector on the
boundary, terminal blocks on the edges, heatsink space for the TO-220s
- Freerouting-based routing script (route_pcb.py) that routes with oversized
tracks/vias and shrinks them, giving 3 mm HV-to-LV and 1.3 mm HV-to-HV
- Custom DRC rules (plasma_dmd_psu.kicad_dru) with documented exceptions
- Wide TO-92 footprints; schematic generator now keeps symbol UUIDs
- DRC: 0 violations, 0 unconnected pads, schematic parity OK
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
mangavalkandClaude Opus 5.5