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Initial commit: plasma DMD driver project

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- Design docs: 12 V DC power supply, safety and bring-up, ESP32 interface, BOM
- PSU schematic (schemdraw) and KiCad 10 carrier-board project with HV net classes
- ESP32 PlatformIO firmware skeleton with HV watchdog toggle
- Reference schematic of the Stern 520-5138-00 display PSU

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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docs/bom.md
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# Bill of materials
Designators match the KiCad project ([../hardware/kicad/](../hardware/kicad/README.md)).
Footprint choices are in [gen_kicad.py](../hardware/kicad/gen_kicad.py).
Prices are rough estimates.
## Modules (AliExpress unless noted)
| Qty | Part | Notes | About |
|---|---|---|---|
| 1 | 12 V 3 A power brick | **Certified brand, from a local retailer** (e.g. Mean Well GST36A12) | €15 |
| 1 | Mini560 5 V fixed buck module | Fixed output, no trim pot | €2 |
| 2 | NCH6100HV nixie HV boost module | Input 9–16 V, output 85–235 V adjustable | €16 |
| 1 | Isolated DC-DC 12 V → 12 V, 6–10 W | e.g. Mornsun URB1212YMD-6WR3 / -10WR3 | €6 |
| 1 | 5 V 1-channel relay module, with optocoupler | Switches the 12 V feed to the HV modules | €2 |
| 1 | Wemos D1 mini ESP32 | | €5 |
## Regulator section (from Mouser / Farnell / Reichelt)
| Qty | Part | Ref (KiCad) | Ref (original Stern board) |
|---|---|---|---|
| 2 | MJE15030 (NPN, TO-220) | Q3, Q6 | Q3, Q5 |
| 1 | MJE15031 (PNP, TO-220) | Q5 | Q4 |
| 1 | MPSA92 (PNP, TO-92) | Q2 | Q1 |
| 1 | MPSA42 (NPN, TO-92) | Q4 | Q2 |
| 2 | 1N5228 (3.9 V zener) | D4, D6 | D3, D4 |
| 1 | 1N4760A (68 V zener) | D5 | D5 |
| 1 | 1N4764A (100 V zener) | D8 | D6 |
| 1 | 1N4743 (13 V zener) | D7 | D7 |
| 2 | 47 kΩ 1 W | R5, R10 | R2, R3 |
| 3 | 1.5 kΩ ½ W | R4, R9, R12 | R4, R5, R10 |
| 2 | 330 kΩ ½ W | R6, R11 | R6, R7 |
| 1 | 2 kΩ 5 W | R13 | R8 |
| 3 | 0.1 µF 500 V film | C6, C8, C9 | C3, C4, C7 |
| 3 | TO-220 heatsink | for Q3, Q5, Q6 | |
## Additions
| Qty | Part | Purpose |
|---|---|---|
| 1 | P6KE15A TVS diode (DO-15) | 12 V input surge protection (D1) |
| 1 | 470 µF 25 V electrolytic | 12 V input bulk (C1) |
| 1 | 100 µF 10 V electrolytic | +5 V bulk (C2) |
| 2 | 22 µF 250 V electrolytic (12.5 mm) | Raw HV rail buffer (C5, C7) |
| 2 | 330 kΩ ½ W | Raw HV rail bleeders (R2, R7) |
| 2 | LED + 100 kΩ 1 W | HV-present indicators (LED1/R3, LED2/R8) |
| 1 | 74HCT245 + DIP socket | 3.3 V → 5 V level shifter |
| 1 | 2N7000, 2 × 1N4148, 100 nF, 10 µF, 100 kΩ | HV watchdog charge pump (Q1, D2, D3, C3, C4, R1) |
| 2 | 1 kΩ 1 W | Series resistors for first power-up |
| 5 | 5×20 mm PCB fuse holders + fuses: 3 A T (F1), 2 × 1 A T (F2, F3), 2 × 100 mA F (F4, F5) | |
| — | Phoenix MKDS 5.08 mm screw terminals: 3 × 2-pin (J1, J6, J7), 2 × 3-pin (J5, J8), 1 × 4-pin (J3), 1 × 5-pin (J4) | Module connections |
| 1 | Molex KK-396 8-pin header (J2) + mating housing | Panel power |
| 1 | 2-pin header + jumper (JP1) | +12 V to panel |
| — | M3 standoffs (H1–H4), 300 V-rated wire, plastic enclosure | |
docs/esp32-interface.md
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# ESP32 interface
Board: **Wemos D1 mini ESP32**, powered from the 5 V rail.
## Level shifting
The panel inputs are 5 V TTL and the ESP32 is 3.3 V. Use a **74HCT245** (HCT only, because it accepts 3.3 V
inputs) powered from 5 V, with DIR tied high (A→B) and OE tied low.
## Pin plan
| Signal (to panel, through 74HCT245) | GPIO | Notes |
|---|---|---|
| Dot clock | 18 | VSPI SCK |
| Serial dot data | 23 | VSPI MOSI |
| Column latch | 17 | |
| Row data | 16 | |
| Row clock | 26 | |
| Display enable | 22 | Pull to *off* state at the 245 input |
| HV watchdog toggle | 21 | Charge pump → relay (see safety.md) |
| +65 V monitor (optional) | 34 | ADC, 2 × 1 MΩ + 33 kΩ divider |
The strapping pins (0, 2, 5, 12, 15) are avoided so nothing twitches during boot.
## Panel data connector
- [ ] Map the panel's 14-pin data connector (signal ↔ pin) for this specific panel before wiring.
## Scanning
- 128 columns × 32 rows, about 120 Hz frame rate (as on WPC).
- Per row: shift 128 bits of dot data (SPI), latch the columns, advance the row (row data is high
for the first row only, then clock the row once per row).
- The panel must never sit with one row lit. Scanning runs continuously, and the HV watchdog is
toggled once per scanned row (about 2 kHz, so the charge pump stays charged).
docs/power-supply.md
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# Power supply design
## Goal
Generate every panel rail from one **12 V DC** input, using cheap modules. Panel voltages are set by
**zener references** (copied from the original Stern board), not by module trim pots. A
mis-set or failed module can't push the panel above its rated voltage.
## The original board (Stern/Sega 520-5138-00)
See [../reference/stern-520-5138-00-display-psu-schematic.jpg](../reference/stern-520-5138-00-display-psu-schematic.jpg).
| CN2 pin | Label | How it is produced | Real value |
|---|---|---|---|
| 8 | +60 V | 88 VAC → D1 → C1 (about +120 V raw) → Q3 (MJE15030) emitter follower, base on D5 68 V zener | about +62–67 V |
| 1 | −120 V | 110 VAC → D2 → C2 (about −150 V raw) → Q4 (MJE15031) follower, base on D6 100 V + D7 13 V zeners | about −112 V |
| 2 | −100 V | Q5 (MJE15030) follower from the D6/D7 junction. Collector to GND via R8 2 kΩ 5 W. | about −100 V |
| 7 | +12 V | Passed through from CN1 | |
| 6 | +5 V | Passed through from CN1 | |
| 4, 5 | GND | | |
- Q1/D3/R2/R4 and Q2/D4/R3/R5: constant-current feeds (about 2 mA) for the zener references.
- R6/R7 (330 kΩ): bleeder resistors. C3/C4/C7: 0.1 µF 500 V decoupling.
## New design
Full schematic: [../hardware/psu-schematic.svg](../hardware/psu-schematic.svg) (PNG alongside).
It is generated from [../hardware/psu_schematic.py](../hardware/psu_schematic.py):
```bash
python -m pip install schemdraw matplotlib
python hardware/psu_schematic.py
```
The schematic's reference designators are new; the notes on the sheet map them to the original board.
Replace the transformer and AC front end (D1, D2, C1, C2, F1, R1) with DC boost modules. Keep the
regulator section as it is.
```
Mains ─► [Certified 12V 3A brick] ─► F 3A ─┬──────────────► +12V (only if the panel uses it)
│
├─► [Mini560 5V buck] ─► +5V ─► panel logic, ESP32, 74HCT245
│
└─► [Relay, NO contact] ◄── HV watchdog (see safety.md)
│
┌──────────────┴──────────────┐
▼ F 1A slow ▼ F 1A slow
[NCH6100HV #1 set 90V] [Isolated 12→12V DC-DC, 6–10W]
│ │
│ [NCH6100HV #2 set 130V]
│ out+ ─► GND
▼ F 100mA, +90V raw ▼ F 100mA, −130V raw
┌───────────────────────────────────────────────────┐
│ Copy of original regulator section: │
│ Q1/Q3/D3/D5/R2/R4 → +62–67V │
│ Q2/Q4/D4/D6/D7/R3/R5 → −112V │
│ Q5/R8/R10 → −100V │
│ R6/R7 bleeders, C3/C4/C7 500V caps │
└───────────────────────────────────────────────────┘
```
### Why the isolated converter
A boost module's output negative is shared with its input ground. Powering module #2 through an
isolated DC-DC lets its output float, so its **+ output is tied to GND** and its − output becomes
−130 V. A second certified 12 V wall adapter would also work.
### Changes compared with the original
- **Removed:** D1, D2, C1, C2, F1, R1 (the boost modules replace the AC front end; the module current
limit plus a 100 mA fast fuse replaces R1).
- **Added:** 10–22 µF / 250 V cap and a 330 kΩ bleeder across each raw HV rail.
- **Added:** HV-present LED (LED + 100 kΩ 1 W) on each raw HV rail.
- **Headroom:** +90 V raw feeding the 68 V-referenced stage, and −130 V raw feeding the
113 V-referenced stage, give the followers enough headroom with modest dissipation. Q3/Q4/Q5 get small heatsinks.
## Open questions
- [ ] Real HV current draw of the panel, so you can size the isolated DC-DC (6 W vs 10 W)
- [ ] Panel power connector pinout and whether +12 V is used
- [ ] Check that NCH6100HV has a usable enable/shutdown pin (otherwise, switch with the relay only, as drawn)
docs/safety.md
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# Safety
About 175 V sits between the +65 V and −112 V rails. Treat every HV node as live until you have
measured it.
## Design measures
1. **Only certified mains equipment.** The 12 V brick is the only mains-connected part. Buy a
certified brand (e.g. Mean Well GST36A12) from a normal retailer, not AliExpress.
2. **Hardware HV watchdog.** The relay on the HV modules' 12 V feed is driven through a charge pump:
```
GPIO21 ──┤├──── A ──►|── B ───┬───────┬──── 2N7000 gate 2N7000 drain ─► relay IN (active-low)
100nF │ 1N4148 │ │ 2N7000 source ─► GND
┴ 1N4148 ═ 10µF ▯ 100k
▲ (anode GND) │ │
GND GND GND
```
Node A gets a diode to GND (cathode at A), and a diode from A to B (anode at A). This rectifies
the toggling signal into a DC voltage on B. A constant high or low level gives no charge.
The firmware toggles GPIO21 once per scanned row (about 2 kHz). If it crashes, or the pin sticks high or low, or
the ESP32 resets, the cap discharges and the relay drops within about 1 s. A stuck row can't burn the panel.
(Check the polarity of your relay module's input. Some are active-low.)
3. **Fail-safe defaults.** The relay is normally open. Put a 10 kΩ pull-down on the watchdog
path. Pull the panel ENABLE line to its *off* state at the 74HCT245 input, so a booting ESP32
can't light anything.
4. **Sequencing.** 5 V comes up, then the ESP32 boots and starts scanning, and only then does the watchdog close the relay.
5. **Fusing.**
| Where | Fuse |
|---|---|
| 12 V input | 3 A |
| Each HV module input | 1 A slow-blow |
| Each raw HV rail | 100 mA fast |
6. **Discharge.** 330 kΩ bleeders on raw and regulated rails. HV-present LEDs are a hint only;
always measure before you touch anything.
7. **Layout.**
- Put all HV parts on one side, with ≥ 3 mm clearance between HV tracks.
- Use wire and caps rated for ≥ 300 V/500 V.
- Use a keyed connector to the panel.
- Close it in a plastic enclosure with no exposed HV.
- Tie all grounds at one point.
8. **Semiconductors from real distributors** (Mouser, Farnell, Reichelt). Fake HV transistors are
common on AliExpress.
## Bring-up procedure
1. Build the 5 V and 12 V side only. Check the voltages.
2. Connect one HV module at a time, with **no load**. Set NCH6100HV #1 to 90 V and #2 to 130 V. Lock the pots with nail varnish.
3. Connect the regulator section, still without the panel. Check for about +65 V, −112 V and −100 V and that the bleeders discharge them.
4. Test the watchdog: stop toggling GPIO21, and the HV must drop within about 1 s.
5. Map the panel's power connector against the measured rails. Get a second check (photo/label).
6. First power-up with the panel: 1 kΩ in series with each HV rail and a running test pattern.
Measure the current per rail, then remove the series resistors.