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Plasma-DMD/hardware/kicad/plasma_dmd_psu.kicad_dru
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(version 1)
# Clearance policy for the PSU carrier board (later rules take priority).
# IPC-2221 B2 (external, uncoated) needs 1.25 mm up to 300 V; we add margin:
# - HV <-> anything else: 3.0 mm (keeps HV well away from the 12 V / 5 V / ESP32 side)
# - HV <-> HV: 1.3 mm (netclass default; up to about 220 V between +90 V and -130 V)
# - HV <-> LV next to a connector pin: 1.8 mm (tracks leaving J2/J5/J7 pins that sit next to other-class pins)
# - inside connectors J*: 0.75 mm (fixed pin pitch; adjacent HV/LV pins differ by <= 53 V at J2, J5/J7 have 2.4 mm)
# - inside the HV electrolytics: 2.5 mm (5 mm pin pitch, 90/130 V)
# - HV <-> HV next to a transistor pin: 1.0 mm (TO-220 pin escape; each transistor only has same-polarity nets around it)
# - inside transistors Q*: 0.6 mm (TO-92 / TO-220 pitch; pins of one transistor differ by < 100 V)
(rule "HV to low voltage"
(condition "A.hasNetclass('HV') && !B.hasNetclass('HV')")
(constraint clearance (min 3.0mm)))
(rule "HV next to connector pins"
(condition "A.hasNetclass('HV') && !B.hasNetclass('HV') && (A.memberOfFootprint('J*') || B.memberOfFootprint('J*'))")
(constraint clearance (min 1.8mm)))
(rule "HV next to transistor pins"
(condition "A.hasNetclass('HV') && B.hasNetclass('HV') && (A.memberOfFootprint('Q*') || B.memberOfFootprint('Q*'))")
(constraint clearance (min 1.0mm)))
(rule "HV inside connectors"
(condition "A.hasNetclass('HV') && A.memberOfFootprint('J*') && B.memberOfFootprint('J*')")
(constraint clearance (min 0.75mm)))
(rule "HV inside transistors"
(condition "A.hasNetclass('HV') && B.hasNetclass('HV') && A.memberOfFootprint('Q*') && B.memberOfFootprint('Q*')")
(constraint clearance (min 0.6mm)))
(rule "HV electrolytic pins"
(condition "(A.memberOfFootprint('C5') && B.memberOfFootprint('C5')) || (A.memberOfFootprint('C7') && B.memberOfFootprint('C7'))")
(constraint clearance (min 2.5mm)))