mangavalk
5fee428ece
Recovered from the 'Projecten' backup in Local\check this. The design files there only differed from this repo by line endings; ram1.mif and the .qip files are needed to regenerate the IP cores but are excluded by .gitignore, so they are added explicitly.
5 lines
275 B
Plaintext
5 lines
275 B
Plaintext
set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"
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set_global_assignment -name IP_TOOL_VERSION "12.1"
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ram1.v"]
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set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ram1.bsf"]
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