commit 01f6ecf396edd8d9790481ec17e316af3524d8de Author: Patrick Valk Date: Mon Nov 14 14:07:01 2016 +0100 init. diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..d8fc955 --- /dev/null +++ b/.gitignore @@ -0,0 +1,64 @@ + +# Created by https://www.gitignore.io/api/alteraquartusii + +### AlteraQuartusII ### +##list taken from http://www.alterawiki.com/wiki/Version_Control (01.10.2015) + +######### Quartus II source files + +# project files: +### project_name.qpf Quartus II project file +### project_name.qsf Quartus constraint file (lists the hardware constraints defined for a project, from the used chip and pinout to timing constraints) +### project_name.qws Quartus Window Settings ? (the configuration of the Quartus gui for the project, may be omitted) + +# top level source files: +### project_name.bdf Block diagram / Schematic file (top level schematic file, there may be many nested files) +### project_name.vhd VHDL file (top level VHDL file) +### project_name.v Verilog file (top level Verilog file) + +# component source files: +### component_name.bsf Block Symbol file (component symbol file) +### component_name.vhd VHDL file (top level VHDL file) +### component_name.v Verilog file (top level Verilog file) + +# SOPC builder project source files (SOPC builder creates many VHDL or Verilog files, that you do not need to store) +### sopc_project_name.ptf the list and configuration of components selected in the SOPC gui +### sopc_project_name.bsf Block Symbol file (SOPC component symbol file, especially if you modified it) + +# Board Description (if you created your own board, the list is incomplete!) +### board_name/class.ptf + +# software source files: +### tbd + +######## Quartus II binary files + +# hardware binary files +### project_name.sof SRAM Object File + +# software binary files +### tbd + +/* +!/*.gitignore +## +!*.qpf +!*.qsf +!*.qws +## +!*.bdf +!*.vhd +!*.v +## +!*.ptf +!*.bsf +## +!**/class.ptf +## +!*.tbd +## +!*.sof +## +## tbd + +!*.tcl \ No newline at end of file diff --git a/8bit_memory.bdf b/8bit_memory.bdf new file mode 100644 index 0000000..ac55685 --- /dev/null +++ b/8bit_memory.bdf @@ -0,0 +1,850 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2012 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "graphic" (version "1.4")) +(pin + (input) + (rect 64 72 232 88) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "Enable" (rect 5 0 38 12)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) +) +(pin + (input) + (rect 64 88 232 104) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "Set" (rect 5 0 21 12)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) +) +(pin + (input) + (rect 64 104 232 120) + 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File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2012 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.2")) +(symbol + (rect 16 16 216 112) + (text "8bit_memory" (rect 5 0 76 14)(font "Arial" (font_size 8))) + (text "inst" (rect 8 80 25 92)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "Enable" (rect 0 0 37 14)(font "Arial" (font_size 8))) + (text "Enable" (rect 21 27 58 41)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)) + ) + (port + (pt 0 48) + (input) + (text "Set" (rect 0 0 18 14)(font "Arial" (font_size 8))) + (text "Set" (rect 21 43 39 57)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)) + ) + (port + (pt 0 64) + (input) + (text "Data[7..0]" (rect 0 0 54 14)(font "Arial" (font_size 8))) + (text "Data[7..0]" (rect 21 59 75 73)(font "Arial" (font_size 8))) + (line (pt 0 64)(pt 16 64)(line_width 3)) + ) + (port + (pt 200 32) + (output) + (text "Out[7..0]" (rect 0 0 48 14)(font "Arial" (font_size 8))) + (text "Out[7..0]" (rect 131 27 179 41)(font "Arial" (font_size 8))) + (line (pt 200 32)(pt 184 32)(line_width 3)) + ) + (port + (pt 200 48) + (output) + (text "savedData[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8))) + (text "savedData[7..0]" (rect 90 43 179 57)(font "Arial" (font_size 8))) + (line (pt 200 48)(pt 184 48)(line_width 3)) + ) + (drawing + (rectangle (rect 16 16 184 80)) + ) +) diff --git a/CPU.bdf b/CPU.bdf new file mode 100644 index 0000000..bdbec75 --- /dev/null +++ b/CPU.bdf @@ -0,0 +1,405 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2012 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "graphic" (version "1.4")) +(pin + (input) + (rect 88 56 256 72) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "set" (rect 5 0 20 12)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 32 72 88 88)) +) +(pin + (input) + (rect 88 96 256 112) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "data" (rect 5 0 26 12)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) 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(pt 14 12)(pt 14 37)) + (arc (pt 31 37)(pt 30 12)(rect 18 12 43 37)) + ) +) +(connector + (pt 456 160) + (pt 456 184) +) +(connector + (pt 456 184) + (pt 464 184) +) +(connector + (pt 456 160) + (pt 536 160) +) +(connector + (pt 544 192) + (pt 544 152) +) +(connector + (pt 544 152) + (pt 456 152) +) +(connector + (pt 456 152) + (pt 456 128) +) +(connector + (pt 456 128) + (pt 464 128) +) +(connector + (pt 528 192) + (pt 544 192) +) +(connector + (pt 528 120) + (pt 536 120) +) +(connector + (pt 448 200) + (pt 464 200) +) +(connector + (pt 448 192) + (pt 440 192) +) +(connector + (pt 368 112) + (pt 368 184) +) +(connector + (pt 368 184) + (pt 376 184) +) +(connector + (pt 448 200) + (pt 448 192) +) +(connector + (pt 280 200) + (pt 376 200) +) +(connector + (pt 280 120) + (pt 280 200) +) +(connector + (pt 256 104) + (pt 288 104) +) +(connector + (pt 264 64) + (pt 256 64) +) +(connector + (pt 352 112) + (pt 368 112) +) +(connector + (pt 368 112) + (pt 464 112) +) +(connector + (pt 264 120) + (pt 280 120) +) +(connector + (pt 280 120) + (pt 288 120) +) +(connector + (pt 728 152) + (pt 712 152) +) +(connector + (pt 648 160) + (pt 640 160) +) +(connector + (pt 536 120) + (pt 536 144) +) +(connector + (pt 536 144) + (pt 536 160) +) +(connector + (pt 264 64) + (pt 264 120) +) +(connector + (pt 640 56) + (pt 624 56) +) +(connector + (pt 640 160) + (pt 640 56) +) +(connector + (pt 600 200) + (pt 576 200) +) +(connector + (pt 576 200) + (pt 576 144) +) +(connector + (pt 536 144) + (pt 576 144) +) +(connector + (pt 576 144) + (pt 648 144) +) +(junction (pt 368 112)) +(junction (pt 536 144)) +(junction (pt 280 120)) +(junction (pt 576 144)) diff --git a/CPU.qpf b/CPU.qpf new file mode 100644 index 0000000..9e8ad77 --- /dev/null +++ b/CPU.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2012 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 12.1 Build 177 11/07/2012 SJ Web Edition +# Date created = 23:14:59 December 28, 2015 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "12.1" +DATE = "23:14:59 December 28, 2015" + +# Revisions + +PROJECT_REVISION = "CPU" diff --git a/CPU.qsf b/CPU.qsf new file mode 100644 index 0000000..fcf0ea7 --- /dev/null +++ b/CPU.qsf @@ -0,0 +1,89 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2012 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 12.1 Build 177 11/07/2012 SJ Web Edition +# Date created = 23:14:59 December 28, 2015 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# CPU_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone II" +set_global_assignment -name DEVICE EP2C20F484C7 +set_global_assignment -name TOP_LEVEL_ENTITY CPU_Main +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 12.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:14:59 DECEMBER 28, 2015" +set_global_assignment -name LAST_QUARTUS_VERSION 12.1 +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_location_assignment PIN_L22 -to Data[0] +set_location_assignment PIN_L21 -to Data[1] +set_location_assignment PIN_M2 -to Data[7] +set_location_assignment PIN_U11 -to Data[6] +set_location_assignment PIN_U12 -to Data[5] +set_location_assignment PIN_W12 -to Data[4] +set_location_assignment PIN_V12 -to Data[3] +set_location_assignment PIN_M22 -to Data[2] +set_location_assignment PIN_R22 -to Set +set_location_assignment PIN_Y21 -to SavedData[7] +set_location_assignment PIN_Y22 -to SavedData[6] +set_location_assignment PIN_W21 -to SavedData[5] +set_location_assignment PIN_W22 -to SavedData[4] +set_location_assignment PIN_V21 -to SavedData[3] +set_location_assignment PIN_V22 -to SavedData[2] +set_location_assignment PIN_U21 -to SavedData[1] +set_location_assignment PIN_U22 -to SavedData[0] +set_location_assignment PIN_R21 -to Enable +set_global_assignment -name BDF_FILE Clk.bdf +set_global_assignment -name BDF_FILE Enabler.bdf +set_global_assignment -name BDF_FILE CPU.bdf +set_global_assignment -name BDF_FILE CPU_Main.bdf +set_global_assignment -name BDF_FILE 8bit_memory.bdf +set_global_assignment -name QIP_FILE clockDevider.qip +set_location_assignment PIN_L1 -to Clk_input +set_location_assignment PIN_R20 -to pin_name1 +set_location_assignment PIN_R19 -to pin_name2 +set_location_assignment PIN_U19 -to pin_name3 +set_location_assignment PIN_Y19 -to pin_name4 +set_location_assignment PIN_T18 -to pin_name5 +set_location_assignment PIN_V19 -to pin_name6 +set_location_assignment PIN_Y18 -to pin_name7 +set_location_assignment PIN_U18 -to pin_name8 +set_global_assignment -name MIF_FILE ram1.mif +set_global_assignment -name QIP_FILE ram1.qip +set_global_assignment -name BDF_FILE "Memory Controller.bdf" +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/CPU.qws b/CPU.qws new file mode 100644 index 0000000..5d7015a Binary files /dev/null and b/CPU.qws differ diff --git a/CPU_Main.bdf b/CPU_Main.bdf new file mode 100644 index 0000000..e7ca3f3 --- /dev/null +++ b/CPU_Main.bdf @@ -0,0 +1,735 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2012 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "graphic" (version "1.4")) +(pin + (input) + (rect 336 256 504 272) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "Set" (rect 5 0 21 12)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 280 272 336 288)) +) +(pin + (input) + (rect 336 224 504 240) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "Enable" (rect 5 0 38 12)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" 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456)) diff --git a/Clk.bdf b/Clk.bdf new file mode 100644 index 0000000..60d8ce5 --- /dev/null +++ b/Clk.bdf @@ -0,0 +1,265 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2012 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. 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b/Clk.bsf new file mode 100644 index 0000000..1d01b32 --- /dev/null +++ b/Clk.bsf @@ -0,0 +1,50 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2012 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.2")) +(symbol + (rect 16 16 152 112) + (text "Clk" (rect 5 0 21 14)(font "Arial" (font_size 8))) + (text "inst" (rect 8 80 25 92)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "Clk_input" (rect 0 0 50 14)(font "Arial" (font_size 8))) + (text "Clk_input" (rect 21 27 71 41)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)) + ) + (port + (pt 136 32) + (output) + (text "Clk_e" (rect 0 0 30 14)(font "Arial" (font_size 8))) + (text "Clk_e" (rect 85 27 115 41)(font "Arial" (font_size 8))) + (line (pt 136 32)(pt 120 32)) + ) + (port + (pt 136 48) + (output) + (text "Clk_s" (rect 0 0 30 14)(font "Arial" (font_size 8))) + (text "Clk_s" (rect 85 43 115 57)(font "Arial" (font_size 8))) + (line (pt 136 48)(pt 120 48)) + ) + (drawing + (rectangle (rect 16 16 120 80)) + ) +) diff --git a/Enabler.bdf b/Enabler.bdf new file mode 100644 index 0000000..4abbfa0 --- /dev/null +++ b/Enabler.bdf @@ -0,0 +1,581 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2012 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "graphic" (version "1.4")) +(pin + (input) + (rect 8 72 176 88) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "Enable" (rect 5 0 38 12)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect -48 88 8 104)) +) +(pin + (bidir) + (rect -8 104 168 120) + (text "BIDIR" (rect 151 0 175 10)(font "Arial" (font_size 6))) + (text "Data[7..0]" (rect 5 0 55 12)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 120 4)(pt 98 4)) + (line (pt 176 8)(pt 124 8)) + (line (pt 120 12)(pt 98 12)) + (line (pt 98 4)(pt 94 8)) + (line (pt 98 12)(pt 94 8)) + (line (pt 120 4)(pt 124 8)) + (line (pt 124 8)(pt 120 12)) + ) + (flipy) + (text "VCC" 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(pt 304 584) + (pt 304 680) + (bus) +) +(connector + (text "Out[7..0]" (rect 293 721 305 764)(font "Arial" )(vertical)) + (pt 304 680) + (pt 304 776) + (bus) +) +(connector + (pt 184 112) + (pt 184 208) + (bus) +) +(connector + (pt 168 112) + (pt 184 112) + (bus) +) +(junction (pt 184 208)) +(junction (pt 184 304)) +(junction (pt 184 400)) +(junction (pt 184 496)) +(junction (pt 184 592)) +(junction (pt 184 688)) +(junction (pt 208 96)) +(junction (pt 208 192)) +(junction (pt 208 288)) +(junction (pt 208 384)) +(junction (pt 208 480)) +(junction (pt 208 576)) +(junction (pt 208 672)) +(junction (pt 304 104)) +(junction (pt 304 200)) +(junction (pt 304 296)) +(junction (pt 304 392)) +(junction (pt 304 488)) +(junction (pt 304 584)) +(junction (pt 304 680)) +(junction (pt 184 112)) diff --git a/Enabler.bsf b/Enabler.bsf new file mode 100644 index 0000000..650ecfe --- /dev/null +++ b/Enabler.bsf @@ -0,0 +1,50 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2012 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.2")) +(symbol + (rect 16 16 160 112) + (text "Enabler" (rect 5 0 47 14)(font "Arial" (font_size 8))) + (text "inst" (rect 8 80 25 92)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "Enable" (rect 0 0 37 14)(font "Arial" (font_size 8))) + (text "Enable" (rect 21 27 58 41)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)) + ) + (port + (pt 144 32) + (output) + (text "Out[7..0]" (rect 0 0 48 14)(font "Arial" (font_size 8))) + (text "Out[7..0]" (rect 75 27 123 41)(font "Arial" (font_size 8))) + (line (pt 144 32)(pt 128 32)(line_width 3)) + ) + (port + (pt 144 48) + (bidir) + (text "Data[7..0]" (rect 0 0 54 14)(font "Arial" (font_size 8))) + (text "Data[7..0]" (rect 69 43 123 57)(font "Arial" (font_size 8))) + (line (pt 144 48)(pt 128 48)(line_width 3)) + ) + (drawing + (rectangle (rect 16 16 128 80)) + ) +) diff --git a/Enabler2.bsf b/Enabler2.bsf new file mode 100644 index 0000000..24da816 --- /dev/null +++ b/Enabler2.bsf @@ -0,0 +1,50 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2012 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.2")) +(symbol + (rect 16 16 160 112) + (text "Enabler" (rect 5 0 47 14)(font "Arial" (font_size 8))) + (text "inst" (rect 8 80 25 92)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "Enable" (rect 0 0 37 14)(font "Arial" (font_size 8))) + (text "Enable" (rect 21 27 58 41)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)) + ) + (port + (pt 144 32) + (bidir) + (text "Out[7..0]" (rect 0 0 48 14)(font "Arial" (font_size 8))) + (text "Out[7..0]" (rect 75 27 123 41)(font "Arial" (font_size 8))) + (line (pt 144 32)(pt 128 32)(line_width 3)) + ) + (port + (pt 144 48) + (bidir) + (text "Data[7..0]" (rect 0 0 54 14)(font "Arial" (font_size 8))) + (text "Data[7..0]" (rect 69 43 123 57)(font "Arial" (font_size 8))) + (line (pt 144 48)(pt 128 48)(line_width 3)) + ) + (drawing + (rectangle (rect 16 16 128 80)) + ) +) diff --git a/Memory Controller.bdf b/Memory Controller.bdf new file mode 100644 index 0000000..f8abe59 --- /dev/null +++ b/Memory Controller.bdf @@ -0,0 +1,455 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2012 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. 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File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2012 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.2")) +(symbol + (rect 16 16 224 144) + (text "Memory Controller" (rect 5 0 107 14)(font "Arial" (font_size 8))) + (text "inst" (rect 8 112 25 124)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "Set Address" (rect 0 0 71 14)(font "Arial" (font_size 8))) + (text "Set Address" (rect 21 27 92 41)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)) + ) + (port + (pt 0 48) + (input) + (text "Set_Data Clk e" (rect 0 0 82 14)(font "Arial" (font_size 8))) + (text "Set_Data Clk e" (rect 21 43 103 57)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)) + ) + (port + (pt 0 64) + (input) + (text "Get Data Clk e" (rect 0 0 80 14)(font "Arial" (font_size 8))) + (text "Get Data Clk e" (rect 21 59 101 73)(font "Arial" (font_size 8))) + (line (pt 0 64)(pt 16 64)) + ) + (port + (pt 0 80) + (input) + (text "Get-Set Data Clk s" (rect 0 0 103 14)(font "Arial" (font_size 8))) + (text "Get-Set Data Clk s" (rect 21 75 124 89)(font "Arial" (font_size 8))) + (line (pt 0 80)(pt 16 80)) + ) + (port + (pt 208 32) + (bidir) + (text "Data[7..0]" (rect 0 0 54 14)(font "Arial" (font_size 8))) + (text "Data[7..0]" (rect 133 27 187 41)(font "Arial" (font_size 8))) + (line (pt 208 32)(pt 192 32)(line_width 3)) + ) + (drawing + (rectangle (rect 16 16 192 112)) + ) +) diff --git a/Memory.bsf b/Memory.bsf new file mode 100644 index 0000000..22d9ba4 --- /dev/null +++ b/Memory.bsf @@ -0,0 +1,64 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2012 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.2")) +(symbol + (rect 16 16 168 112) + (text "CPU" (rect 5 0 28 14)(font "Arial" (font_size 8))) + (text "inst" (rect 8 80 25 92)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "enable" (rect 0 0 37 14)(font "Arial" (font_size 8))) + (text "enable" (rect 21 27 58 41)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)) + ) + (port + (pt 0 48) + (input) + (text "set" (rect 0 0 17 14)(font "Arial" (font_size 8))) + (text "set" (rect 21 43 38 57)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)) + ) + (port + (pt 0 64) + (input) + (text "data" (rect 0 0 24 14)(font "Arial" (font_size 8))) + (text "data" (rect 21 59 45 73)(font "Arial" (font_size 8))) + (line (pt 0 64)(pt 16 64)) + ) + (port + (pt 152 32) + (output) + (text "out" (rect 0 0 17 14)(font "Arial" (font_size 8))) + (text "out" (rect 114 27 131 41)(font "Arial" (font_size 8))) + (line (pt 152 32)(pt 136 32)) + ) + (port + (pt 152 48) + (output) + (text "savedData" (rect 0 0 61 14)(font "Arial" (font_size 8))) + (text "savedData" (rect 70 43 131 57)(font "Arial" (font_size 8))) + (line (pt 152 48)(pt 136 48)) + ) + (drawing + (rectangle (rect 16 16 136 80)) + ) +) diff --git a/clockDevider.bsf b/clockDevider.bsf new file mode 100644 index 0000000..60a3286 --- /dev/null +++ b/clockDevider.bsf @@ -0,0 +1,57 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2012 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.2")) +(symbol + (rect 0 0 144 64) + (text "clockDevider" (rect 37 0 123 16)(font "Arial" (font_size 10))) + (text "inst" (rect 8 48 25 60)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 26 25 49 38)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)) + ) + (port + (pt 144 40) + (output) + (text "q[25..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) + (text "q[25..0]" (rect 89 33 123 46)(font "Arial" (font_size 8))) + (line (pt 144 40)(pt 128 40)(line_width 3)) + ) + (drawing + (text "up counter" (rect 84 22 211 55)(font "Arial" )) + (line (pt 16 16)(pt 16 48)) + (line (pt 16 16)(pt 128 16)) + (line (pt 16 48)(pt 128 48)) + (line (pt 128 16)(pt 128 48)) + (line (pt 0 0)(pt 146 0)) + (line (pt 146 0)(pt 146 66)) + (line (pt 0 66)(pt 146 66)) + (line (pt 0 0)(pt 0 66)) + (line (pt 16 26)(pt 22 32)) + (line (pt 22 32)(pt 16 38)) + (line (pt 0 0)(pt 0 0)) + (line (pt 0 0)(pt 0 0)) + (line (pt 0 0)(pt 0 0)) + (line (pt 0 0)(pt 0 0)) + ) +) diff --git a/clockDevider.v b/clockDevider.v new file mode 100644 index 0000000..e26dce7 --- /dev/null +++ b/clockDevider.v @@ -0,0 +1,111 @@ +// megafunction wizard: %LPM_COUNTER% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: LPM_COUNTER + +// ============================================================ +// File Name: clockDevider.v +// Megafunction Name(s): +// LPM_COUNTER +// +// Simulation Library Files(s): +// lpm +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 12.1 Build 177 11/07/2012 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2012 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module clockDevider ( + clock, + q); + + input clock; + output [25:0] q; + + wire [25:0] sub_wire0; + wire [25:0] q = sub_wire0[25:0]; + + lpm_counter LPM_COUNTER_component ( + .clock (clock), + .q (sub_wire0), + .aclr (1'b0), + .aload (1'b0), + .aset (1'b0), + .cin (1'b1), + .clk_en (1'b1), + .cnt_en (1'b1), + .cout (), + .data ({26{1'b0}}), + .eq (), + .sclr (1'b0), + .sload (1'b0), + .sset (1'b0), + .updown (1'b1)); + defparam + LPM_COUNTER_component.lpm_direction = "UP", + LPM_COUNTER_component.lpm_port_updown = "PORT_UNUSED", + LPM_COUNTER_component.lpm_type = "LPM_COUNTER", + LPM_COUNTER_component.lpm_width = 26; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACLR NUMERIC "0" +// Retrieval info: PRIVATE: ALOAD NUMERIC "0" +// Retrieval info: PRIVATE: ASET NUMERIC "0" +// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" +// Retrieval info: PRIVATE: CLK_EN NUMERIC "0" +// Retrieval info: PRIVATE: CNT_EN NUMERIC "0" +// Retrieval info: PRIVATE: CarryIn NUMERIC "0" +// Retrieval info: PRIVATE: CarryOut NUMERIC "0" +// Retrieval info: PRIVATE: Direction NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" +// Retrieval info: PRIVATE: ModulusCounter NUMERIC "0" +// Retrieval info: PRIVATE: ModulusValue NUMERIC "50000000" +// Retrieval info: PRIVATE: SCLR NUMERIC "0" +// Retrieval info: PRIVATE: SLOAD NUMERIC "0" +// Retrieval info: PRIVATE: SSET NUMERIC "0" +// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: nBit NUMERIC "26" +// Retrieval info: PRIVATE: new_diagram STRING "1" +// Retrieval info: LIBRARY: lpm lpm.lpm_components.all +// Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP" +// Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "26" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock" +// Retrieval info: USED_PORT: q 0 0 26 0 OUTPUT NODEFVAL "q[25..0]" +// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 26 0 @q 0 0 26 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL clockDevider.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clockDevider.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clockDevider.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clockDevider.bsf TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clockDevider_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clockDevider_bb.v FALSE +// Retrieval info: LIB_FILE: lpm diff --git a/memory.bdf b/memory.bdf new file mode 100644 index 0000000..b378238 --- /dev/null +++ b/memory.bdf @@ -0,0 +1,1321 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2012 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. 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File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2012 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.2")) +(symbol + (rect 0 0 216 128) + (text "ram1" (rect 94 0 128 16)(font "Arial" (font_size 10))) + (text "inst" (rect 8 112 25 124)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "data[7..0]" (rect 0 0 53 14)(font "Arial" (font_size 8))) + (text "data[7..0]" (rect 4 18 47 31)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 88 32)(line_width 3)) + ) + (port + (pt 0 48) + (input) + (text "wren" (rect 0 0 30 14)(font "Arial" (font_size 8))) + (text "wren" (rect 4 34 28 47)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 88 48)) + ) + (port + (pt 0 64) + (input) + (text "address[7..0]" (rect 0 0 75 14)(font "Arial" (font_size 8))) + (text "address[7..0]" (rect 4 50 66 63)(font "Arial" (font_size 8))) + (line (pt 0 64)(pt 88 64)(line_width 3)) + ) + (port + (pt 0 112) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 4 98 27 111)(font "Arial" (font_size 8))) + (line (pt 0 112)(pt 80 112)) + ) + (port + (pt 216 32) + (output) + (text "q[7..0]" (rect 0 0 35 14)(font "Arial" (font_size 8))) + (text "q[7..0]" (rect 183 18 211 31)(font "Arial" (font_size 8))) + (line (pt 216 32)(pt 136 32)(line_width 3)) + ) + (drawing + (text "8 bits" (rect 109 23 191 153)(font "Arial" )(vertical)) + (text "256 words" (rect 120 13 212 173)(font "Arial" )(vertical)) + (text "Block type: AUTO" (rect 48 114 170 239)(font "Arial" )) + (line (pt 104 24)(pt 136 24)) + (line (pt 136 24)(pt 136 96)) + (line (pt 136 96)(pt 104 96)) + (line (pt 104 96)(pt 104 24)) + (line (pt 118 58)(pt 123 63)) + (line (pt 118 62)(pt 123 57)) + (line (pt 88 27)(pt 96 27)) + (line (pt 96 27)(pt 96 39)) + (line (pt 96 39)(pt 88 39)) + (line (pt 88 39)(pt 88 27)) + (line (pt 88 34)(pt 90 36)) + (line (pt 90 36)(pt 88 38)) + (line (pt 80 36)(pt 88 36)) + (line (pt 96 32)(pt 104 32)(line_width 3)) + (line (pt 88 43)(pt 96 43)) + (line (pt 96 43)(pt 96 55)) + (line (pt 96 55)(pt 88 55)) + (line (pt 88 55)(pt 88 43)) + (line (pt 88 50)(pt 90 52)) + (line (pt 90 52)(pt 88 54)) + (line (pt 80 52)(pt 88 52)) + (line (pt 96 48)(pt 104 48)) + (line (pt 88 59)(pt 96 59)) + (line (pt 96 59)(pt 96 71)) + (line (pt 96 71)(pt 88 71)) + (line (pt 88 71)(pt 88 59)) + (line (pt 88 66)(pt 90 68)) + (line (pt 90 68)(pt 88 70)) + (line (pt 80 68)(pt 88 68)) + (line (pt 96 64)(pt 104 64)(line_width 3)) + (line (pt 80 112)(pt 80 36)) + (line (pt 0 0)(pt 217 0)) + (line (pt 217 0)(pt 217 130)) + (line (pt 0 130)(pt 217 130)) + (line (pt 0 0)(pt 0 130)) + (line (pt 0 0)(pt 0 0)) + (line (pt 0 0)(pt 0 0)) + (line (pt 0 0)(pt 0 0)) + (line (pt 0 0)(pt 0 0)) + ) +) diff --git a/ram1.v b/ram1.v new file mode 100644 index 0000000..bd3fc35 --- /dev/null +++ b/ram1.v @@ -0,0 +1,172 @@ +// megafunction wizard: %RAM: 1-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: ram1.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 12.1 Build 177 11/07/2012 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2012 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module ram1 ( + address, + clock, + data, + wren, + q); + + input [7:0] address; + input clock; + input [7:0] data; + input wren; + output [7:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [7:0] sub_wire0; + wire [7:0] q = sub_wire0[7:0]; + + altsyncram altsyncram_component ( + .address_a (address), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .q_a (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.init_file = "ram1.mif", + altsyncram_component.intended_device_family = "Cyclone II", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 256, + altsyncram_component.operation_mode = "SINGLE_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.widthad_a = 8, + altsyncram_component.width_a = 8, + altsyncram_component.width_byteena_a = 1; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +// Retrieval info: PRIVATE: AclrByte NUMERIC "0" +// Retrieval info: PRIVATE: AclrData NUMERIC "0" +// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "0" +// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "ram1.mif" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: RegAddr NUMERIC "1" +// Retrieval info: PRIVATE: RegData NUMERIC "1" +// Retrieval info: PRIVATE: RegOutput NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SingleClock NUMERIC "1" +// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" +// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "8" +// Retrieval info: PRIVATE: WidthData NUMERIC "8" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: INIT_FILE STRING "ram1.mif" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" +// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" +// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" +// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" +// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL ram1.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram1.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram1.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram1.bsf TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram1_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ram1_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf